IC Data Sheets
8.
8.7
TMDS261PAGT (IC U1503)
Figure 8-7 Internal block diagram and pin configuration
HPD_
S
INK
VCC
R
INT
Clock Detect
R
INT
VCC
R
INT
TMD
S
Rx
R
INT
VCC
R
INT
Clock Detect
R
INT
VCC
R
INT
TMD
S
Rx
R
INT
Dx+_1
Dx–_1
CLK+_1
CLK–_1
Dx+_2
Dx–_2
CLK+_2
CLK–_2
Rx
Tx
Rx
Tx
S
CL1
S
DA1
Rx
Tx
Rx
Tx
S
CL2
S
DA2
V
Sa
dj
Dx+_
S
INK
Dx–_
S
INK
CLK+_
S
INK
CLK–_
S
INK
TMD
S
Tx
TMD
S
Tx
Tx
Rx
Tx
Rx
S
DA_
S
INK
S
CL_
S
INK
S
1/
S
CL
S
2/
S
DA
I2C_
S
EL
Clock Detect
LP
TMD
S
Rx
w/ AEQ
TMD
S
Rx
w/ AEQ
HPD1
HPD2
2:1
MUX
a
nd
2
Pin Confi
g
uration
Block Dia
g
ram
1
8
2
8
0_
3
06_090420.ep
s
090519
1
2
3
4
5
6
7
8
9
10
11
12
1
3
14
15
16
NC
NC
GND
NC
NC
VCC
NC
NC
GND
NC
NC
VCC
NC
NC
GND
V
sa
dj
7
1
8
1
9
1
0
2
21
22
3
2
4
2
5
2
6
2
7
2
8
2
2
9
0
3
1
3
2
3
S
_
+
2
D
K
NI
2
DK
NI
S
_
–
C
VC
NI
S
_
+
1
DK
NI
S
_
–
1
DK
N
GD
_
+
0
D
K
NI
S
NI
S
_
–
0
DK
C
C
V
L
C
K
NI
S
_
+
K
S
_
–
K
L
C
K
NI
GD
N
_
L
C
S
K
NI
S
I
S
_
A
D
S
K
N
S
_
D
P
H
K
NI
1
S
L
C
S
/
4
8
47
46
45
44
4
3
42
41
40
3
9
38
3
7
3
6
3
5
3
4
33
D2+_1
D2–_1
VCC
D1+_1
D1–_1
GND
D0+_1
D0–_1
VCC
CLK+_1
CLK–_1
S
CL1
S
DA1
HPD1
I2C_
S
EL
S
2/
S
DA
4
6
3
6
2
6
1
6
0
6
9
5
8
5
7
5
6
5
5
5
4
5
5
3
2
5
1
5
0
5
9
4
C
N
+
2
D2
_
2
_
–
2
D
V
C
C
+
1
D
2
_
2
_
–
1
D
D
N
G
+
0
D2
_
2
_
–
0
D
V
C
C
K
L
C2
_
+
K
L
C2
_
–
2
L
C
S
S
2
A
D
D
P
H2
P
L
TMD
S
261
64-pin TQFP
PAG-64