IC Data Sheets
8.
8.6
MX25L1605DM2I-12G (IC U4402)
Figure 8-6 Internal block diagram and pin configuration
Addre
ss
Gener
a
tor
Memory Arr
a
y
P
a
ge B
u
ffer
Y-Decoder
X-Decoder
D
a
t
a
Regi
s
ter
S
RAM
B
u
ffer
S
I/
S
IO0
S
CLK
Clock Gener
a
tor
S
t
a
te
M
a
chine
Mode
Logic
S
en
s
e
Amplifier
HV
Gener
a
tor
O
u
tp
u
t
B
u
ffer
S
O/
S
IO1
C
S
#,
WP#/ACC,
HOLD#
Pin Confi
g
uration
Block Dia
g
ram
1
8
2
8
0_
3
05_090420.ep
s
090519
1
2
3
4
C
S
#
S
O/
S
IO1
WP#/ACC
GND
8
7
6
5
VCC
HOLD#
S
CLK
S
I/
S
IO0