Circuit Diagrams and PWB Layouts
10.
SSB: SPDIF/Debug/RS232 Int.
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN
OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
C
DEBUG / R
S
2
3
2 INTERFACE
1JE
3
C9
1JEA E5
1JEB E6
1JEC E7
1JED E
8
1JEE E9
1M15 D1
2J11 E2
2J12 E2
D
E
A
B
6J11 E4
6J12 D4
CONNECTOR
UART
RXD2
4
5
6
7
D
E
F
G
H
I
J
2
3
8
TXD2
S
ERVICE
12
8
9
10
A
B
C
RXD1
F
G
H
A
owner.
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
IJ12 D4
IJ5
3
B2
S
PDIF
S
PDIF/De
bu
g/R
S
2
3
2 Interf
a
ce
TXD1
FOR DEVELOPMENT ONLY
IJ54 B
3
1JEF E9
IJ57 C4
IJ5
8
C
3
IJE1 B6
2J61 C
3
2J62 B
3
2JE1 B
8
2JE2 B6
C
D
E
1J10 E2
1J11 E2
1JE1 C9
1
2
3
3
JE2 C
8
3
JE
3
C
8
3
JE4 C
8
3
JE5 C
8
10
11
I
4
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
B
C
UART1
6
5
4
1
3
A
B
C
D
E
4
5
6
7
FJEB C9
FJEC B7
FJED C9
FJEE C9
12
IJE7 C6
IJE
8
C7
IJE9 C6
IJEA C7
IJEB C6
IJE2 B7
IJE
3
B6
IJE4 B7
IJE5 B6
2JE
3
B
8
3
J51 C4
3
J5
3
C4
3
JE0 D6
3
JE1 D6
7
8
9
2
1
1
3
7J50 B2
7JE2 B7
5
6
7
1
3
9
10
1
2
3
FJ11 E
3
FJ12 D
3
FJ1
3
E1
FJEA C9
8
9
10
11
IJ56 C
3
3
J5
3
120R
IJE6 C6
2JE4 B
8
2JE5 B6
3
J11 E
3
3
J12 D
3
3
J50 B2
IJEC C7
IJED C6
IJEE C7
IJEF D5
J
3
2
3
J11
100R
BAV99 COL
6J12
1
9
4
1
1
1
7
0
1
2
6
16
1
3
4
5
15
2
1
3
1
8
7JE2
Φ
R
S
2
3
2
S
T
3
2
3
2C
4
+
3
V
3
-
S
TANDBY
1
2
3
5
74HCT1G0
8
GW
7J50
FJEC
1
2
3
4
5
IJEA
1JE
3
2JE5
100n
EMC HOLE
1JEF
IJE1
3
JE0
100R
FJ11
IJE9
2J12
100p
2J11
100p
EMC HOLE
1JED
EMC HOLE
1JEE
2JE4
100n
EMC HOLE
1JEB
1J11
FJ1
3
IJE6
EMC HOLE
1JEC
8
IJE5
1
2
3
4
5
7
1M15
M
S
J-0
3
5-10A B AG PPO
1J10
IJEF
3
J51
220R
2J61
100n
IJ5
3
2J62
100n
IJ54
100n
2JE2
100n
2JE
3
IJE
3
IJEE
1JEA
EMC HOLE
100R
3
JE4
FJEA
100R
3
JE1
IJE2
IJE4
IJ5
8
2R2
3
J50
2
IJEB
BAV99 COL
6J11
1
3
100n
A
3
1
3
0
2JE1
200
8
-04-1
8
YiPing G
u
o
DC
3
07
3
67
200
8
-04-25
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 2007
200
8
-02-2
8
1
8
3
PC
33
2
4
3
PB522
S
ETNAME
CHN
CLA
SS
_NO
S
UPER
S
.
1
NAME
DATE
CHECK
3
1
3
9 2
83
3
00
3
PCB
S
B PB522 He
a
lthc
a
re
PB522
FJED
3
100R
3
JE
3
100R
3
JE2
4
5
IJEC
FJEB
1JE1
1
2
3
IJE
8
+
3
V
3
IJE7
IJ56
IJ57
100R
3
J12
3
JE5
100R
+
3
V
3
-
S
TANDBY
FJ12
IJED
+
3
V
3
-
S
TANDBY
IJ12
DV-B0_UART2-RX
RXD
RXD_PC
TXD_PC
FJEE
DV-B1_UART2-TX
TXD
S
PDIF-OUT
S
PI-OUT
1
8
710_517_090
8
21.ep
s
090
8
24