Circuit Diagrams and PWB Layouts
10.
SSB: Debug
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN
OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
C
5
I
J
11
10
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
J
2
FOR DEVELOPMENT ONLY
6
IAM4 B
3
IAM5 B
3
IAM6 A4
IAM7 B4
IAM
8
B4
IAM9 B4
6
7
7
1
8
3
AM
3
B5
3
AM4 C5
C
D
E
9
10
11
12
1
3
9AM1 C
3
9AM2 E4
FAM0 B6
FAM1 B6
1
2
3
4
FAM
8
D5
FAM9 E5
FAMA E5
FAMB E5
FAMC C6
FAMD C6
I
A
1
3
12
S
T40 DEBUG LINK
9
8
RE
S
3
4
5
2
3
4
5
UART
3
IAM
3
B
3
4
5
6
7
8
A
IAMA B
3
IAMB B
3
D
E
A
B
B
C
3
AM5 C5
3
AM6 C
3
3
AM7 C4
F
G
H
7AM1-2 E4
9AM0 D5
F
FAM2 B6
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
owner.
H
FAM7 D5
G
FAME E6
FAMJ D5
2AM4 B
3
3
AM0 D5
3
AM1 B
3
3
AM2 B5
C
D
E
1AM0 B6
1AM1 B6
1
1AM2 D6
2AM0 A4
2AM1 A
3
2AM2 A5
2AM
3
B5
UART4
IAM0 A
3
IAM1 B
3
IAM2 B
3
DEBUG
6
7
8
1
2
3
B
C
B
A
3
AM
8
E4
7AM0 A4
7AM1-1 D
3
D
E
FAM
3
D5
FAM4 D5
FAM5 D5
FAM6 D5
9
8
4
1
1
1
7
0
1
2
6
16
+
3
V
3
1
3
4
5
15
2
1
3
1
Φ
R
S
2
3
2
S
T
3
2
3
2C
7AM0
2AM
3
100n
100R
3
AM
3
FAMB
IAMA
2
3
4
5
FAM4
1AM1
BM0
3
B-
S
R
SS
-TBT
1
2AM4
100n
3
AM2
100R
IAM1
IAM6
FAM7
RE
S
IAM5
9AM0
+
3
V
3
IAM
3
74LVC07APW
7AM1-2
3
7
14
4
+
3
V
3
IAM7
IAM
8
14
2
IAM0
74LVC07APW
7AM1-1
1
7
FAMA
10K
3
AM7
3
AM1
100R
FAM1
FAM0
100n
2AM1
FAM
3
FAMD
IAM4
IAM9
IAMB
+
3
V
3
FAMJ
100R
3
AM4
FAM6
4
5
FAM5
1AM0
BM0
3
B-
S
R
SS
-TBT
1
2
3
100R
100n
3
AM5
2AM2
3
AM6
100R
9AM1
2AM0
10K
3
AM
8
100n
3
AM0
33
R
IAM2
FAM9
9AM2
3
4
5
6
7
8
9
12
1
3
14
15
16
17
1
8
19
2
20
1AM2
5-147279-5
1
10
11
FAM
8
FAMC
YiPing G
u
o
200
8
-04-1
8
3
+
3
V
3
A
3
PB522
PCB
S
B PB522 He
a
lthc
a
re
3
1
3
9 2
83
3
00
3
CHECK
DATE
NAME
1
S
UPER
S
.
CLA
SS
_NO
2
2
5
B
P
E
M
A
N
T
E
S
N
H
C
4
3
3
PC
33
2
40
200
8
-02-2
8
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 2007
200
8
-04-25
DC
3
07
3
67
FAME
1
3
0
FAM2
BUF-R
S
T-TARGETn
JTAG-TDI
JTAG-TDO
R
S
T-TARGETn
JTAG-TR
S
Tn
TRIG-OUT
TRIG-IN
JTAG-TM
S
A
S
EBRKn
JTAG-TCK
RXD-A
S
C2
TXD-A
S
C
3
RXD-A
S
C
3
TXD-A
S
C2
1
8
710_5
3
9_090
8
24.ep
s
090
8
24