10.
Circuit Diagrams and PWB Layouts
SSB: Interface STI7100
C
R0OUT
G0OUT
B0OUT
IDUMPR0
VIDDIGOUT
VIDDIGOUTYC
AUDANA
AUDANAOUT
AUDOUT
IDUMPY1
REXT0
REXT1
GNDAREXT0
GNDAREXT1
VIDANA
VIDANA
VIDANA
VIDANA
VIDANA
VIDANA
TMD
S
AUDDIG
AUDPCMOUT
TX0P
TX0N
TX1P
TX1N
TX2P
TX2N
TMD
S
REF
DATAIN
D
S
TRBIN
DLRCLKIN
0
1
2
H
S
YNC
VBGFIL
IREF
S
CLK
LRCLK
PCMCLK
4
S
PDIF
PLEFT
MLEFT
PRIGHT
MRIGHT
V
S
YNC
0
1
2
3
4
5
6
7
8
9
10
11
12
1
3
14
15
IDUMPG0
IDUMPB0
C1OUT
CV1OUT
Y1OUT
IDUMPC1
IDUMPCV1
3
TXCP
TXCN
12
1
3
A
2AC0 D2
2AC1 B6
2AC2 C6
2AC
3
C7
3
AC
3
C4
3
AC4 C4
3
AC5 D4
3
AC6 B6
3
AC7 C6
IAC1 C7
IAC2 C4
1
2
3
4
5
3
4
5
D
E
F
6
7
8
A
B
C
6
7
8
1
2
J
D
E
A
B
C
D
E
10
11
9
10
3
AC1 D1
3
AC2 C4
I
J
3
AC
8
C7
3
AC9 D4
3
ACA C6
3
ACB C6
3
ACC E4
7A00-1 B
3
7AC0 B6
FAC0 D4
1
3
1
IAC
3
D4
IAC4 D2
IAC5 D2
9
B
C
H
I
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
2
3
4
A
B
C
D
E
5
6
COMPEN
S
ATION RE
S
I
S
TOR
7
1
8
G
H
11
12
2
3
4
5
6
7
8
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
owner.
F
G
1
u
0
2AC0
560R
3
AC1
12K
3
AC2
IAC1
100n
2AC
3
3
AC
8
6
8
R
3
ACA
1
8
0R
+
3
V
3
+
3
V
3
+
3
V
3
BC
8
47BW
7AC0
2AC1
1
u
0
3
AC6
1K2
1K0
3
AC7
3
ACB
2K2
2AC2
100n
3
ACC
100R
H
33
U
3
0
T
3
1
R
3
1
R
3
0
P
3
1
P
3
0
N
3
1
K
3
4
K
33
J
3
4
J
33
H
3
4
D
33
B
33
D
3
4
A
3
1
A
3
2
B
3
4
M
33
M
3
4
L
3
4
L
33
T
3
0
U
33
E
3
4
A
3
4
C
3
4
F
3
4
B
3
1
B
3
2
E
33
A
33
C
33
F
33
E24
D24
T
3
2
T
3
4
T
33
R
3
4
R
33
P
3
4
P
33
U
3
4
C2
8
D29
E2
8
D2
8
E26
D26
A25
B25
C25
D25
E25
S
TI7100YWC
7A00-1
Φ
AV
INTERFACE
C27
B27
B2
8
A27
A2
8
FAC0
1
NAME
DATE
CHECK
3
1
3
9 2
83
3
00
3
+
3
V
3
TMD
S
1
3
0
3
200
8
-04-1
8
YiPing G
u
o
DC
3
07
3
67
200
8
-04-25
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 2007
200
8
-02-2
8
3
7
3
PC
33
2
4
3
PB522
S
ETNAME
CHN
CLA
SS
_NO
S
UPER
S
.
3
AC9
100R
PCB
S
B PB522 He
a
lthc
a
re
PB522
A
3
IAC
3
IAC2
IAC4
IAC5
3
AC5
22K
3
AC4
12K
22K
3
AC
3
PCMOUT2
PCMOUT
3
PCMOUT4
DRXC+
DRXC-
DRX0+
DRX0-
DRX1+
DRX1-
DRX2+
DRX2-
1
8
710_5
3
6_090
8
24.ep
s
090
8
24
Interf
a
ce
S
TI7100