Circuit Diagrams and PWB Layouts
10.
SSB: PNX5100 - SDRAM
N
P
N
P
N
P
N
P
P
N
VREF
IREF
C
S
B
CKE
ODT
WEB
CA
S
B
RA
S
B
BA2
10
11
12
1
3
BA1
BA0
12
11
10
9
8
7
6
5
4
3
2
1
0
2
3
24
25
26
27
2
8
29
3
0
3
1
0
1
2
3
D
A
DQM
DQ
S
0
DQ
S
1
DQ
S
2
DQ
S3
CLK
22
21
20
19
1
8
17
16
15
14
0
1
2
3
4
5
6
7
8
9
C
12
11
10
9
8
7
6
5
4
3
0
1
2
3
4
5
6
7
8
9
10
11
12
CK
VDDL
VREF
V
SS
DL
14
VDDQ
Q
S
S
V
S
S
V
BA
A
LDQ
S
UDQ
S
NC
DQ
CKE
WE
ODT
RA
S
1
C
S
CA
S
0
0
1
2
VDD
LDM
UDM
15
1
3
12
11
10
9
8
7
6
5
4
3
0
1
2
3
4
5
6
7
8
9
10
11
12
CK
VDDL
VREF
V
SS
DL
14
VDDQ
Q
S
S
V
S
S
V
BA
A
LDQ
S
UDQ
S
NC
DQ
CKE
WE
ODT
RA
S
1
C
S
CA
S
0
0
1
2
VDD
LDM
UDM
15
1
3
2C1
8
F6
3
C0
3
H2
3
C04 H9
3
C05-1 G6
3
C05-2 G6
3
C05-
3
H6
3
C05-4 H6
3
C06-1 G5
3
C06-2 G5
3
C06-
3
H
3
12
H
2C44-1 F9
2C44-2 F9
2C44-
3
F10
2C44-4 F10
3
C00 C2
3
C01 C2
BD 12NC :
3
1
3
9_12
3
_644
33
MULTI 12NC :
3
1
3
9_12
3
_6442
3
CELL 12NC :
8
2
3
9_125_147
83
3
C06-4 H2
J
14
15
I
2C00 E4
2C01 C5
2C02 E5
2C1
3
F5
2C14 F5
2C15 F5
2C16 F6
2C17 F6
" XC
3
0
~
XC
3
Z "
6
M
11
1
2
3
4
5
6
7
H
G
G
P
" XC00
~
XC0Z "
P
D
E
F
G
F
1
3
14
1
2
3
4
5
6
7
8
3
C02 C
3
2C19 F6
D
E
5
B
9
3
20
19
2
1
M
C
" XC20
~
XC2Z "
8
9
C
15
17
10
1
10
N
10
11
" XC20
~
XC2Z "
" XC40
~
XC4Z "
9
L
2C29 E11
2C
3
0 E11
2C
3
2 F12
9
10
16
I
12
A
K
F
E
11
12
1
3
14
A
11
4
3
C
3
0-1 H12
12
1
3
B
A
D
1
8
19
owner.
J
14
2
" XC10
~
XC1Z "
3
4
N
B
C
D
E
F
G
H
I
A
B
C
1
8
K
7
6
All right
s
re
s
erved. Reprod
u
ction in whole or in p
a
rt
s
I
8
17
H
2C
33
F12
2C
3
4 F12
2C
3
5 F12
2C
3
6 F12
2C
38
F1
3
2C
3
9 H1
3
2C40 H6
2C41-1 F2
2C41-2 F2
2C41-
3
F2
2C41-4 F2
3
C09-
3
G5
3
C09-4 H6
3
C10 C5
3
C11 H6
3
C12 H
3
3
C1
3
H2
3
C20 A10
3
C21 B10
8
16
3
C27-1 G12
3
C
3
0-2 H12
3
C
3
0-
3
I9
3
C
3
0-4 H9
3
C
3
1 G1
3
3
C
3
2 H1
3
7C00-
8
A6
7C01 F
3
7C02 F10
FC02 C
3
FC05 B12
3
C22 A12
3
C2
3
B12
3
C25-1 G1
3
3
C25-2 G1
3
3
C25-
3
H12
3
C25-4 H1
3
3
C26-1 G1
3
3
C26-2 G12
3
C26-
3
G12
3
C26-4 G1
3
7
20
3
C09-2 H5
PNX5100 -
S
DRAM
O
FC06 B10
2C42-1 F
3
2C42-2 F
3
2C42-
3
F
3
2C42-4 F
3
2C4
3
-1 F
8
2C4
3
-2 F
8
2C4
3
-
3
F9
2C4
3
-4 F9
O
1
3
5
3
C27-2 G12
3
C27-
3
H9
3
C27-4 H9
3
C2
8
-1 H1
3
3
C2
8
-2 G12
3
C2
8
-
3
H12
3
C2
8
-4 H1
3
i
s
prohi
b
ited witho
u
t the written con
s
ent of the copyright
L
3
C07-1 G6
3
C07-2 G5
3
C07-
3
G5
3
C07-4 G6
3
C0
8
-1 H5
3
C0
8
-2 H5
3
C0
8
-
3
G6
3
C09-1 H6
2
7
33
R
3
C0
8
-2
4
5
1
8
33
R
3
C06-4
33
R
3
C25-1
2C
3
0
1
u
0
PNX5100-DDR2-VREF-CTRL
PNX5100-DDR2-VREF-DDR
+1V
8
-PNX5100
2C02
1
u
0
4
5
33
R
3
C27-4
3
C
3
2
33
R
100R
3
C02
RE
S
2C19
22
u
100n
2C15
+1V
8
-PNX5100
2C4
3
-4
100n
45
+1V
8
-PNX5100
3
6
33
R
3
C
3
0-
3
3
K
3
3
C10
E25
E2
3
E24
N2
3
K2
3
K24
P24
U24
RE
S
W24
AB2
3
AA26
AA2
3
G26
G2
3
W25
W26
Y2
3
Y24
E26
F24
J2
3
J24
D2
3
AC26
G24
D24
AC25
U26
AB26
V26
H26
G25
J26
Y25
K26
D25
H25
D26
F2
3
H24
P26
L2
3
Y26
AB25
AA24
AC24
AC2
3
V2
3
AB24
V24
F26
T24
L25
R24
L26
M2
3
R26
T25
N24
L24
U2
3
P25
N26
U25
T26
K25
M24
N25
T2
3
M26
Φ
DDR2
PNX5100E
7C00-
8
PNX5100-DDR2-VREF-DDR
2C1
8
100n
200
8
-10-17
A2
PCB
S
B
SS
B BD
TV54
3
_2K9
3
1
3
9 12
3
644
3
CHECK
*
*
*
*
*
*
*
*
E
M
A
N
T
E
S
N
H
C
25
3
PC
33
2
22
200
8
-10-17
ROYAL PHILIP
S
ELECTRONIC
S
N.V. 200
8
****
***
*****
S
V
2009-06-1
8
DC
3
94240
Vincent Y
a
p / Lee CW
2009-01-16
2
3
1
3
0
10
2
2009-02-25
-- -- --
DATE
NAME
3
S
UPER
S
.
1
CLA
SS
_NO
5K6 1
%
5
4
3
C00
3
C07-4
33
R
1
8
33
R
3
C0
8
-1
3
C0
3
150R
3
C
3
1
1
8
33
R
3
6
100n
2C4
3
-1
33
R
3
C06-
3
2C16
100n
2C14
100n
100n
2C1
3
+1V
8
-PNX5100
PNX5100-DDR2-VREF-CTRL
3
C22
1K0
1
%
22
u
2C
38
B2
B
8
D2
D
8
E7
F2
F
8
H2
K
3
G7
J2
A
3
E
3
J
3
N1
P9
J7
A7
H
8
J1
A9
G9
C1
C
3
C7
C9
E9
G1
G
3
K7
B
3
B7
A
8
A1
E1
J9
M9
R1
C2
F
3
F7
E
8
A2
E2
L1
R
3
R7
R
8
K9
D1
D9
B1
B9
H7
H
3
H1
H9
F1
F9
C
8
L
3
L7
J
8
K2
K
8
L
8
G
8
G2
D7
D
3
R2
M7
N2
N
8
N
3
N7
P2
P
8
P
3
L2
Φ
S
DRAM
M
8
M
3
M2
P7
7C02
HYB1
8
TC512160B2F-
3S
100n
2C
33
100n
2C17
2C01
100n
100n
2C
3
5
4
5
33
R
3
C
3
0-4
4
5
33
R
3
C05-4
33
R
3
C11
3
C12
33
R
2C
3
6
100n
FC02
150R
3
C04
2C
3
4
100n
3
C21
1K0
1
%
3
6
33
R
3
C0
8
-
3
8
1
3
3
C09-1
33
R
3
C07-
3
33
R
6
3
C07-2
33
R
7
2
1
%
8
20R
3
C01
3
C05-2
2
7
33
R
7
2
3
C09-2
33
R
2
7
33
R
3
C27-2
3
C2
8
-1
33
R
1
8
3
6
100n
2C41-
3
8
1
3
C26-1
33
R
3
6
D
8
E7
F2
F
8
H2
K
3
100n
2C42-
3
P9
J7
A7
H
8
B2
B
8
D2
G1
G
3
G7
J2
A
3
E
3
J
3
N1
J1
A9
G9
C1
C
3
C7
C9
E9
B7
A
8
A1
E1
J9
M9
R1
E2
L1
R
3
R7
R
8
K9
K7
B
3
F9
C
8
C2
F
3
F7
E
8
A2
D9
B1
B9
H7
H
3
H1
H9
F1
J
8
K2
K
8
L
8
G
8
G2
D7
D
3
D1
N7
P2
P
8
P
3
L2
L
3
L7
M
3
M2
P7
R2
M7
N2
N
8
N
3
S
DRAM
Φ
HYB1
8
TC512160B2F-
3S
7C01
M
8
+1V
8
-PNX5100
1K0
3
C20
1
%
3
C26-4
33
R
5
4
33
R
6
3
4
5
3
C09-
3
33
R
3
C25-4
1
8
100n
2C41-1
2C
3
2
100n
2C
3
9
100n
33
R
5
4
PNX5100-DDR2-VREF-DDR
45
3
C09-4
2C42-4
100n
FC05
33
R
3
C1
3
3
C2
8
-
3
33
R
3
6
1
8
33
R
3
C27-1
2C41-4
100n
45
27
2C4
3
-2
100n
33
R
6
3
3
C26-
3
33
R
3
C06-2
2
7
3
C07-1
33
R
8
1
27
2C41-2
100n
3
C06-1
1
8
2
7
33
R
3
C2
8
-2
33
R
2
7
1
8
33
R
3
C
3
0-2
3
6
33
R
3
C
3
0-1
33
R
3
C25-
3
100n
2C44-2
27
1
%
2C40
1K0
3
C2
3
100n
33
R
3
C25-2
2
7
3
C26-2
33
R
7
2
45
2C44-4
100n
3
6
FC06
100n
2C44-
3
1
8
3
6
33
R
3
C05-1
100n
2C4
3
-
3
6.
3
V
33
0
u
2C29
2C00
33
0
u
6.
3
V
RE
S
3
C2
8
-4
33
R
4
5
3
6
1
8
33
R
3
C05-
3
3
6
100n
2C44-1
33
R
3
C27-
3
27
8
2C42-2
100n
100n
2C42-1
1
PNX5100-DDR2-DQ
S
0_P
PNX5100-DDR2-DQ
S
1_P
PNX5100-DDR2-DQ
S
0_N
PNX5100-DDR2-ODT
PNX5100-DDR2-RA
S
PNX5100-DDR2-DQM
3
PNX5100-DDR2-DQ
S3
_P
PNX5100-DDR2-DQ
S3
_N
PNX5100-DDR2-WE
PNX5100-DDR2-D22
PNX5100-DDR2-D2
3
PNX5100-DDR2-D24
PNX5100-DDR2-D25
PNX5100-DDR2-DQM2
PNX5100-DDR2-DQ
S
2_P
PNX5100-DDR2-DQ
S
2_N
PNX5100-DDR2-D
3
0
PNX5100-DDR2-D
3
1
PNX5100-DDR2-D1
8
PNX5100-DDR2-D19
PNX5100-DDR2-D20
PNX5100-DDR2-D21
PNX5100-DDR2-C
S
PNX5100-DDR2-D16
PNX5100-DDR2-D17
PNX5100-DDR2-D26
PNX5100-DDR2-D27
PNX5100-DDR2-D2
8
PNX5100-DDR2-D29
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A
8
PNX5100-DDR2-A9
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
PNX5100-DDR2-CA
S
PNX5100-DDR2-CLK_P
PNX5100-DDR2-CKE
PNX5100-DDR2-CLK_N
PNX5100-DDR2-DQ
S
2_N
PNX5100-DDR2-DQ
S
2_P
PNX5100-DDR2-DQ
S3
_N
PNX5100-DDR2-DQ
S3
_P
PNX5100-DDR2-ODT
PNX5100-DDR2-RA
S
PNX5100-DDR2-WE
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
PNX5100-DDR2-A2
PNX5100-DDR2-A
3
PNX5100-DDR2-A4
PNX5100-DDR2-D4
PNX5100-DDR2-D5
PNX5100-DDR2-D6
PNX5100-DDR2-D7
PNX5100-DDR2-D
8
PNX5100-DDR2-D9
PNX5100-DDR2-DQM0
PNX5100-DDR2-DQM1
PNX5100-DDR2-DQM2
PNX5100-DDR2-DQM
3
PNX5100-DDR2-DQ
S
0_N
PNX5100-DDR2-DQ
S
0_P
PNX5100-DDR2-DQ
S
1_N
PNX5100-DDR2-DQ
S
1_P
PNX5100-DDR2-D12
PNX5100-DDR2-D1
3
PNX5100-DDR2-D14
PNX5100-DDR2-D15
PNX5100-DDR2-D16
PNX5100-DDR2-D17
PNX5100-DDR2-D19
PNX5100-DDR2-D1
8
PNX5100-DDR2-D2
PNX5100-DDR2-D22
PNX5100-DDR2-D2
3
PNX5100-DDR2-D20
PNX5100-DDR2-D21
PNX5100-DDR2-D24
PNX5100-DDR2-D
3
0
PNX5100-DDR2-D26
PNX5100-DDR2-D25
PNX5100-DDR2-D2
8
PNX5100-DDR2-D
3
1
PNX5100-DDR2-D
3
PNX5100-DDR2-D27
PNX5100-DDR2-D29
PNX5100-DDR2-A
3
PNX5100-DDR2-A4
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A
8
PNX5100-DDR2-A9
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
PNX5100-DDR2-CA
S
PNX5100-DDR2-CKE
PNX5100-DDR2-CLK_N
PNX5100-DDR2-CLK_P
PNX5100-DDR2-C
S
PNX5100-DDR2-D0
PNX5100-DDR2-D1
PNX5100-DDR2-D10
PNX5100-DDR2-D11
PNX5100-DDR2-D
8
PNX5100-DDR2-D9
PNX5100-DDR2-DQM0
PNX5100-DDR2-ODT
PNX5100-DDR2-RA
S
PNX5100-DDR2-DQM1
PNX5100-DDR2-DQ
S
1_N
PNX5100-DDR2-WE
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
PNX5100-DDR2-A2
PNX5100-DDR2-D11
PNX5100-DDR2-D12
PNX5100-DDR2-D1
3
PNX5100-DDR2-D14
PNX5100-DDR2-D15
PNX5100-DDR2-D2
PNX5100-DDR2-D
3
PNX5100-DDR2-D4
PNX5100-DDR2-D5
PNX5100-DDR2-D6
PNX5100-DDR2-D7
PNX5100-DDR2-A0
PNX5100-DDR2-A1
PNX5100-DDR2-A10
PNX5100-DDR2-A11
PNX5100-DDR2-A12
PNX5100-DDR2-A2
PNX5100-DDR2-A
3
PNX5100-DDR2-A4
PNX5100-DDR2-A5
PNX5100-DDR2-A6
PNX5100-DDR2-A7
PNX5100-DDR2-A
8
PNX5100-DDR2-A9
PNX5100-DDR2-BA0
PNX5100-DDR2-BA1
PNX5100-DDR2-CA
S
PNX5100-DDR2-CLK_P
PNX5100-DDR2-CKE
PNX5100-DDR2-CLK_N
PNX5100-DDR2-C
S
PNX5100-DDR2-D0
PNX5100-DDR2-D1
PNX5100-DDR2-D10
1
8
670_521_090911
.ep
s
090911
Содержание 40PFL8664H/12
Страница 48: ...IC Data Sheets EN 48 Q548 1E LB 8 2009 Dec 18 ...