Service Modes, Error Codes, and Fault Finding
5.
Figure 5-4 “Off/Stand-by” to “Semi Stand-by” flowchart (part 1)
1
8
440_216
a
_090227.ep
s
09111
8
No
EJTAG pro
b
e
connected ?
No
Ye
s
Rele
as
e AVC
s
y
s
tem re
s
et
Feed w
a
rm
b
oot
s
cript
Cold
b
oot?
Ye
s
No
S
et I²C
s
l
a
ve
a
ddre
ss
of
S
t
a
nd
b
y µP to (A0h)
An EJTAG pro
b
e (e.g. WindPower ICE pro
b
e) c
a
n
b
e
connected for Lin
u
x Kernel de
bu
gging p
u
rpo
s
e
s
.
Thi
s
will
a
llow
a
cce
ss
to NVM
a
nd
NAND FLA
S
H
a
nd c
a
n not
b
e done
e
a
rlier
b
ec
aus
e the FLA
S
H need
s
to
b
e in Write Protect
as
long
as
the
su
pplie
s a
re not
a
v
a
il
ab
le.
Detect EJTAG de
bu
g pro
b
e
(p
u
lling pin of the pro
b
e interf
a
ce to
gro
u
nd
b
y in
s
erting EJTAG pro
b
e)
Rele
as
e AVC
s
y
s
tem re
s
et
Feed cold
b
oot
s
cript
Rele
as
e AVC
s
y
s
tem re
s
et
Feed initi
a
lizing
b
oot
s
cript
di
sab
le
a
live mech
a
ni
s
m
Initi
a
li
s
e I/O pin
s
of the
s
t-
b
y µP:
-
S
witch re
s
et-AVC LOW (re
s
et
s
t
a
te)
-
S
witch WP-N
a
ndFl
as
h LOW (protected)
-
S
witch re
s
et-
s
y
s
tem LOW (re
s
et
s
t
a
te)
-
S
witch re
s
et-5100 LOW (re
s
et
s
t
a
te)
-
S
witch re
s
et-Ethernet LOW (re
s
et
s
t
a
te)
- keep re
s
et-NVM high, A
u
dio-re
s
et
a
nd A
u
dio-M
u
te-Up HIGH
Off
S
t
a
nd
b
y
Su
pply
s
t
a
rt
s
r
u
nning.
All
s
t
a
nd
b
y
su
pply volt
a
ge
s b
ecome
a
v
a
il
ab
le.
s
t-
b
y µP re
s
et
s
S
t
a
nd
b
y or
Protection
M
a
in
s
i
s a
pplied
-
S
witch A
u
dio-Re
s
et high.
It i
s
low in the
s
t
a
nd
b
y mode if the
s
t
a
nd
b
y
mode l
as
ted longer th
a
n 10
s
.
s
t
a
rt key
b
o
a
rd
s
c
a
nning, RC detection. W
a
ke
u
p re
as
on
s a
re
off.
If the protection
s
t
a
te w
as
left
b
y
s
hort circ
u
iting the
S
DM pin
s
, detection of
a
protection condition d
u
ring
s
t
a
rt
u
p will
s
t
a
ll the
s
t
a
rt
u
p. Protection condition
s
in
a
pl
a
ying
s
et will
b
e ignored. The protection mode will
not
b
e entered.
S
witch LOW the RE
S
ET-NVM line to
a
llow
a
cce
ss
to NVM. (Add
a
2m
s
del
a
y
b
efore trying to
a
ddre
ss
the NVM to
a
llow correct NVM
initi
a
liz
a
tion, thi
s
i
s
no i
ssu
e in thi
s s
et
u
p, the del
a
y i
s au
tom
a
tic
a
lly
covered
b
y the
a
rchitect
u
r
a
l
s
et
u
p)
Rele
as
e Re
s
et-PNX5100.
PNX5100 will
s
t
a
rt
b
ooting.
Thi
s
10m
s
del
a
y i
s s
till pre
s
ent to give
s
ome rel
a
x
a
tion
to the
su
pplie
s
. (The PCI
a
r
b
iter on the PNX5100 i
s
never
us
ed
a
nd i
s
not the re
as
on
a
nymore)
S
witch HIGH the WP-N
a
ndFl
as
h to
a
llow
a
cce
ss
to NAND Fl
as
h
Thi
s
en
ab
le
s
the +
3
V
3 a
nd +5V converter. A
s a
re
su
lt,
a
l
s
o +5V-t
u
ner, +2V5, +1V
8
-PNX
8
541
a
nd
+1V
8
-PNX5100 (if pre
s
ent)
b
ecome
a
v
a
il
ab
le.
Confirm
a
tion received from NXP th
a
t there doe
s
not need to
b
e
a
del
a
y
b
etween the ri
s
e of the +1V2
a
nd the +
3
V
3
. Only
re
qu
irement i
s
to h
a
ve the +1V2
b
efore or
a
t the
sa
me time
as
the +
3
V
3
. 150m
s
del
a
y i
s
deleted.
Del
a
y of 50m
s
needed
b
ec
aus
e of the l
a
tency of
the detect-1 circ
u
it. Thi
s
del
a
y i
s a
l
s
o needed for
the PNX5100. The re
s
et of the PNX5100
s
ho
u
ld
only
b
e rele
as
ed 10m
s a
fter powering the IC.
Detect2
s
ho
u
ld
b
e polled on the
s
t
a
nd
a
rd 40m
s
interv
a
l
a
nd
s
t
a
rt
u
p
s
ho
u
ld
b
e contin
u
ed when
detect2
b
ecome
s
high.
+12V, +24V
s
, AL
a
nd Bolt-on power
i
s s
witched on, followed
b
y the +1V2 DCDC converter
En
ab
le the
su
pply detection
a
lgorithm
No
Ye
s
Detect-1 I/O line
High?
S
witch ON Pl
a
tform
a
nd di
s
pl
a
y
su
pply
b
y
s
witching
LOW the
S
t
a
nd
b
y line.
En
ab
le the DCDC converter for +
3
V
3 a
nd
+5V. (ENABLE-
3
V
3
)
Volt
a
ge o
u
tp
u
t error:
L
a
yer1: 2
L
a
yer2: 1
8
No
Detect2 high received
within 2
s
econd
s
?
Power-OK error:
L
a
yer1:
3
L
a
yer2: 16
Enter protection
Ye
s
W
a
it 50m
s
Enter protection
Ye
s
No
Detect-2 I/O line
High?
Di
sab
le
3
V
3
,
s
witch
s
t
a
nd
b
y
line high
a
nd w
a
it 4
s
econd
s
Del
a
y 1.5
s
econd
b
efore checking detect2 line
if the detect2_del
a
y_fl
a
g i
s s
et
S
et detect2_del
a
y_fl
a
g
Re
s
et detect2_del
a
y_fl
a
g
C
a
ref
u
ll we don’t hit thi
s
error
directly if the del
a
y fl
a
g i
s s
et.
W
a
it fixed time of 15m
s
Detect2 high?
Ye
s
No
Detect-1 I/O line
High?
W
a
it 50m
s
No
Ye
s
If the
su
pply i
s
hicking, the fir
s
t detect2 co
u
ld
b
e po
s
itive (12V
s
till pre
s
ent), followed
b
y
neg
a
tive
Su
pply-f
au
lt (
a
lre
a
dy low). Adding
a
fixed del
a
y
b
ring
s us b
ehind thi
s
del
a
y g
a
p.
The
s
e check
s
prevent the
s
et from going in to
s
t
a
nd
b
y on the f
a
l
s
e error condition where the
fir
s
t
3
V
3
i
s
neg
a
tive
b
ec
aus
e of
a
hick
u
p,
a
ltho
u
gh the 12V w
as ab
o
u
t to re
a
ppe
a
r.
Bec
aus
e of thi
s
re
a
ppe
a
r
a
nce, the 12V check
i
s
OK which wo
u
ld c
aus
e protection. If we w
a
it
50m
s
, the
3
V
3 s
ho
u
ld
b
e
ba
ck
as
well.
Detect-2 I/O line
High?
Ye
s
No
Re
s
et detect2_del
a
y_fl
a
g
Only
us
ef
u
ll in c
as
e of PNX5100 pre
s
ent. To
a
void
diver
s
ity in
s
t
a
nd
b
y µP, the re
s
et-PNX5100 will
s
till
b
e
s
witched
b
y the
s
t
a
nd
b
y µP.
To: 1
8
440_216
b
_090227.ep
s
To: 1
8
440_216
b
_090227.ep
s
W
a
it 10 m
s
Содержание 40PFL8664H/12
Страница 48: ...IC Data Sheets EN 48 Q548 1E LB 8 2009 Dec 18 ...
