Circuit Diagrams and PWB Layouts
10.
10-2-11
B03C, UMAC 1 DDR3
19280_011_120322.eps
120322
UMAC 1 DDR3
B03C
B03C
2011-12-16
UMAC 1 DDR3
3
2011-11-24
2
8204 000 9238
7
8
BA0
9
10
11
12
13
VREFDQ
VREFCA
14
DQS
0
1
TDQS
VDD
CAS
CK
CK
CKE
CS
WE
RESET
0
NC
DQS
VSS
VSSQ
3
4
5
6
7
VDDQ
TDQS
DM
ODT
RAS
BA2
BA1
2
1
2
3
4
5
6
ZQ
AP
BC
A
DQ
7
8
BA0
9
10
11
12
13
VREFDQ
VREFCA
14
DQS
0
1
TDQS
VDD
CAS
CK
CK
CKE
CS
WE
RESET
0
NC
DQS
VSS
VSSQ
3
4
5
6
7
VDDQ
TDQS
DM
ODT
RAS
BA2
BA1
2
1
2
3
4
5
6
ZQ
AP
BC
A
DQ
3J21
100R
2J
83
10n
2J
8
1
10n
10n
2J
8
7
F9
J2
J10
L2
B
3
B9
C10
D2
D10
H4
H9
J9
E2
A2
L10
N2
N10
A9
B2
D9
F
3
D
8
G
3
G9
K2
K10
M2
M10
B10
C2
E
3
E10
H2
H10
J8
N1
G2
F4
N3
A8
A
3
A10
D3
E8
C4
D4
A1
N11
A4
A11
F2
F10
G10
G8
H3
B8
B4
C8
C3
C9
E4
E9
L9
L3
M9
M3
N9
M4
J3
K9
J4
G4
F8
K4
L8
H8
M8
K8
N4
N8
L4
K3
7J01
H5TQ2G83BFR
100R
3J2T
100R
3J2C
2J1E
10n
10
u
2J24
2J
8
6
10n
3J19
100R
2J1H
10n
DB32
DB33
100R
3J1Y
100R
3J28
+1V5-M1
10n
2J
8
2
DB38
3
J15
1K0
100R
3J2F
100R
3J2P
100n
2J16
FJ09
2J1T
100n
DB31
100R
3J1G
100R
3J1F
DB48
DB91
2J1
8
100n
DB54
+1V5-M1
3J1A
100R
3J2H
100R
DB42
3J1H
100R
+1V5-M1
2J22
10
u
DB40
DB39
3J2M
100R
DB55
3J1W
100R
100R
3J2G
3J2R
100R
2J
8
4
+1V5-M1
10n
DB57
DB58
DB56
DB01
DB06
DB34
DB35
100R
3J2J
2J15
100n
100R
3J20
100R
3J27
2J1J
10n
2J1D
10n
10n
2J12
DB90
RES
DB52
3J2E
100R
DB36
16V
2J27
47
u
3J1S
100R
3J1R
100R
100n
2J20
3J2S
100R
+1V5-M1
DBA1
DB59
DB99
100R
3J1U
DB62
100R
3J2K
100R
3J1K
3J2A
100R
100R
3J1T
100R
3J2Q
100R
3J1L
100R
3J2L
DBA7
DBA6
10
u
10n
2J1C
2J25
100R
3J18
3J1D
100R
3J29
100R
3J2B
100R
DB94
DB93
DB49
2J21
100n
100n
2J1U
1K0
2J1
S
3
J11
100n
100n
100n
2J1R
2J17
DB41
DB51
DB43
3J22
100R
3J1M
100R
DBA5
DBA4
DBA2
DBA3
3J1P
DB53
100R
3J26
100R
+1V5-M1
2J1A
100n
3
J16
DB64
75R
DB63
3J1N
100R
3J25
100R
+1V5-M1
2J
8
9
10n
3J1V
100R
3J2D
100R
FJ08
DB98
DB96
DB97
DB95
DB50
3J1E
100R
+1V5-M1
3J1J
100R
3J2N
100R
1K0
3
J12
10n
2J1F
10n
2J1K
100n
2J19
100R
3J1C
10n
2J1G
L2
B
3
B9
C10
D2
D10
H4
H9
L10
N2
N10
A9
B2
D9
F
3
F9
J2
J10
K10
M2
M10
B10
C2
E
3
E10
J9
E2
A2
N1
G2
F4
N3
A8
A
3
A10
D
8
G
3
G9
K2
C4
D4
A1
N11
A4
A11
F2
F10
H2
H10
J8
H3
B8
B4
C8
C3
C9
E4
E9
D3
E8
M3
N9
M4
J3
K9
J4
G4
F8
G10
G8
L8
H8
M8
K8
N4
N8
L4
K3
L9
L3
M9
7J02
H5TQ2G83BFR
K4
+1V5-M1
2J1V
100n
100R
3J1Z
3
J14
100n
2J1B
1K0
10n
2J
8
5
+1V5-M1
240R
3
J1
3
3
J10
240R
100n
2J14
3
J17
75R
2J
88
10n
100R
3J24
100R
3J23
100n
2J1Z
2J1W
100n
100R
3J1B
M1-MCLK0
M1-MCLK0#
M1-MA13
M1-MA15
M1-DQM1
M1-MD5
M1-MD6
M1-MD1
M1-MD2
M1-MD7
M1-MD4
M1-MD3
M1-MA15
M1-MD13
M1-MD8
M1-MD9
M1-DQS1
M1-DQS#1
M1-DQS0
M1-DQS#0
M1-MD0
M1-RESET#
M1-MD14
M1-MD15
M1-MD10
M1-MD11
M1-MD12
M1-MA11
M1-MA12
M1-MA13
M1-MA14
M1-MA15
M1-BA0
M1-BA1
M1-BA2
M1-RAS#
M1-CAS#
M1-WE#
M1-CS#
M1-ODT
M1-CKE
M1-MA0
M1-MA1
M1-MA2
M1-MA3
M1-MA4
M1-MA5
M1-MA6
M1-MA7
M1-MA8
M1-MA9
M1-MA10
M1-CKE
M1-MCLK0#
M1-CS#
M1-MA14
M1-ODT
M1-RESET#
DDR-MVREF12
M1-WE#
M1-RAS#
DDR-MVREF12
M1-MA2
M1-MA3
M1-MA4
M1-MA5
M1-MA6
M1-MA7
M1-MA8
M1-MA9
M1-BA0
M1-BA1
M1-BA2
M1-CAS#
M1-MCLK0
DDR-MVREF11
M1-WE#
M1-RAS#
M1-DQM0
DDR-MVREF11
M1-MA0
M1-MA1
M1-MA10
M1-MA11
M1-MA12
M1-MA0
M1-MA1
M1-MA10
M1-MA11
M1-MA12
M1-MA13
M1-MA14
M1-MA2
M1-MA3
M1-MA4
M1-MA5
M1-MA6
M1-MA7
M1-MA8
M1-MA9
M1-BA0
M1-BA1
M1-BA2
M1-CAS#
M1-MCLK0
M1-CKE
M1-MCLK0#
M1-CS#
M1-ODT
M1-RESET#