10.
Circuit Diagrams and PWB Layouts
SPI-Buffer
1
8
770_56
8
_100125.ep
s
100125
S
PI-B
u
ffer
B06D
B06D
2009-10-22
2
8
204 000
8
957
LVD
S
Non DVB
S
G
3
1
2
3
EN2
3
EN1
3
GE
3
B4
3
GE4 B
3
7GE0 B
3
*
B
u
ffer
IGE0 B
3
IGE1 D2
B
2GE0 A2
3
GE0-1 B4
3
GE0-
3
B4
3
GE1-
3
B4
3
GE1-4 B
3
3
GE2 A4
9GE0-1 C
3
9GE0-2 C
3
9GE0-
3
D
3
9GE1 C
3
9GE2 D
3
3
4
7GE1 A4
C
D
A
*
Direct
5
6
1
2
3
4
5
6
C
D
**
5
4
A
B
*
9GE
3
D
3
1
2
*
9GE0-4
9GE2
9GE
3
9GE0-
3
6
3
IGE0
1
8
3
6
47R
3
GE0-1
47R
3
GE0-
3
10K
3
GE2
7GE1
PDTC114EU
15
14
1
3
12
11
1
10
19
20
2
3
4
5
6
7
8
9
1
8
17
16
7GE0
74LVC245A
47R
3
GE
3
RE
S
9GE1
9GE0-2
7
2
IGE1
47R
3
GE1-4
RE
S
5
4
47R
RE
S
6
3
3
GE4
+
3
V
3
47R
3
GE1-
3
100n
2GE0
+
3
V
3
BL-
S
PI-
S
DI
PNX-
S
PI-CLK
BL-
S
PI-CLK
BL-
S
PI-
S
DO
PNX-
S
PI-C
S
-BLn
BL-
S
PI-C
S
n
PNX-
S
PI-
S
DI
PNX-
S
PI-
S
DI
PNX-
S
PI-C
S
-AMBIn
AMBI-
S
PI-C
S
-OUTn_R2-R
BL-
S
PI-CLK
AMBI-
S
PI-CLK-OUT-R
PNX-
S
PI-CLK
PNX-
S
PI-
S
DO
AMBI-
S
PI-
S
DI-OUT_G1-R
BL-
S
PI-
S
DO
AMBI-
S
PI-
S
DO-OUT-R
BL-
S
PI-
S
DI
PNX-
S
PI-
S
DO
PNX-
S
PI-C
S
Bn