10.
Circuit Diagrams and PWB Layouts
PNX85500 Control
1
8
770_764_10072
8
.ep
s
10072
8
PNX
8
5500 Control
B01E
B01E
2010-0
3
-12
3
2010-02-01
2
8
204 000 90
8
1
TUNER, HDMI & CI
D
C
S
W
HOLD
V
SS
Q
VCC
S
CL
ADR
0
1
2
S
DA
WC
U
S
E ONLY
1
2
3
4
MAIN NVM
3
F59 E
3
B
C
D
8
9
7F52 B2
7F5
3
B7
7F54-1 C7
E
F
A
3
F66 B7
8
9
D
E
F
1F51 F
8
LEVEL
7F5
8
D1
9CH0 C7
FF04 C4
3
F60 E
3
3
F62 D5
1
S
DA
1F52 D
8
FF57 E2
5
6
7
FF6
3
E4
FF64 F7
FF65 F4
3
F5
8
E1
IF50 B
3
IF51 B1
IF52 B
3
2
3
4
3
F5
3
C6
3
F54 D7
A
3
F6
3
E5
3
F64 F5
3
F65 F5
IF55 C6
3
F67 B6
3
F6
8
C7
3
F69 D7
IF59 E1
IF61 C4
IF62 C4
7F54-2 C7
B
C
2F52 B1
2F5
3
D6
2F5
8
D2
3
F51 B1
3
F52 B
3
FF29 C4
FF55 E
3
FF56 E
3
S
HIFTED
UP
FF66 F4
5
6
7
IF57 C7
FOR
IF5
8
D2
DEBUG / R
S
2
3
2 INTERFACE
S
CL
IF5
3
B
3
IF54 C
3
DEBUG ONLY
FF5
8
C7
FF61 D4
FF62 D7
DEBUG
IF56 C7
3
F65
IF5
8
IF62
100R
IF59
3
F60
100R
FF65
3
4
5
3
F51
10K
1F52
1
2
IF52
+
3
V
3
3
F5
3
IF5
3
10K
10K
3
F66
RE
S
+
3
V
3
-
S
TANDBY
10K
3
F67
RE
S
IF54
+
3
V
3
-
S
TANDBY
5
3
4
RE
S
7F54-2
BC
8
47BPN(COL)
1
2
3
4
5
6
7
1F51
3
F5
8
10K
IF51
9CH0
RE
S
IF57
RE
S
1
u
0
2F5
3
3
F54
1K0
RE
S
FF6
3
100R
3
F64
100R
FF56
3
F6
3
10K
3
F52
FF55
3
F59
100R
IF61
FF29
10K
3
F69
RE
S
RE
S
PDTA114EU
FF04
7F5
3
FF64
3
F62
100R
FF57
+
3
V
3
IF50
100n
2F52
RE
S
IF55
+
3
V
3
IF56
FF5
8
+
3
V
3
-
S
TANDBY
+
3
V
3
RE
S
2F5
8
100n
6
1
RE
S
7F54-1
BC
8
47BPN(COL)
2
8
4
7
FF66
7F5
8
1
2
3
6
5
+
3
V
3
-
S
TANDBY
(
8
K ×
8
)
Φ
EEPROM
3
FF61
+5V
6
5
7
2
1
8
4
7F52
M25P05-AVMN6
FLA
S
H
512K
Φ
47K
3
F6
8
FF62
RE
S
BOO
S
T-PWM
BACKLIGHT-BOO
S
T
S
DM
S
PI-PROG
RE
S
ET-
S
TBYn
S
PI-PROG
S
CL-UP-MIP
S
S
CL-
SS
B
S
DA-
SS
B
TXD-UP
RXD-UP
PNX-
S
PI-CLK
PNX-
S
PI-
S
DO
PNX-
S
PI-C
S
Bn
PNX-
S
PI-
S
DI
PNX-
S
PI-WPn
S
DA-UP-MIP
S