VSBC-32
Functional Description
ID 21168, Rev. 04
Page 2 - 19
©
PEP Modular Computers GmbH
2.6.5
Bus Error Timers
The VSBC-32(E) provides an on-board bus error timer and a VMEbus error timer.
There are three cases of bus error
:
On-Board Bus Error Timer
An 8µs timeout on-board timer monitors the cycle lengths of data transfers to and from
locations beyond the CPU data bus buffer, including on-board I/O, VMEbus, SRAM and
CXC. After a timeout occurs, it generates an on-board bus error signal for error termina-
tion. This timer is enabled/disabled via the board control/status register, which also sup-
plies a timeout status bit in order to identify bus errors generated by the on-board bus
error timer.
During VMEbus cycles the on-board bus error timer is reset as soon as the VSBC-32(E)
gains VMEbus ownership, i.e. the time gap between a VMEbus request and the starting
of the VMEbus cycle is monitored by the on-board bus error timer. The VMEbus cycles
themselves are monitored by the separate VMEbus error timer.
VMEbus Error Timer
In addition to the on-board bus error timer, the VSBC-32(E) provides a bus monitor for
the VMEbus. A 128µs timer monitors VMEbus data transfer cycle lengths and generates
a VMEbus bus error signal BERR* for error termination. This error is enabled and dis-
abled via the VMEbus control/status register which also supplies a timeout status bit in
order to identify bus errors genrated by the bus monitor.
For a complete map of the VMEbus control/status register please refer to the relating
section in the Configuration chapter of this manual.
Table 2-6: Bus Error Types
Cause
Timeout
Enable / Disable
Reserved address BERR0
100ns
Permanently enabled
On-board BERR1
8µ s
Enable / disable possible,
set in board control register
VMEbus BERR2
128µ s
Enable / disable possible,
set in VMEbus control register
Note...
The internal MC68(EN)360 bus error timer (hardware watchdog
timer) is not used on the VSBC-32(E). Therefore, it should
remain disabled (default setting).
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