VSBC-32
Introduction
ID 21168, Rev. 04
Page 1 - 10
©
PEP Modular Computers GmbH
1.3.3
Board Layouts
Figure 1-3: VSBC-32(E) Board Diagram (front)]
FLASH/EPROM:
Upper Data:
D8-D15, even Byte addresses
Lower Data:
D0-D7, odd Byte addresses
BDM:
Background Debug Mode.
SRAM
FLASH/EPROM
(Upper Data)
1
16
17
32
FLASH/EPROM
(Lower Data)
1
16
17
32
1
6
7
12
BDM
CPU / Serial
Communications
Controller
ST2B
ST2C
1
7
SI Piggyback
1
49
2
50
BU3
1
49
2
50
BU4
Memory Piggyback
EEPROM
ST2A
1
7
J14
3
1
2
J13
3
1
2
J11
J12
J9
J10
J6
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