VSBC-32
Functional Description
ID 21168, Rev. 04
Page 2 - 13
©
PEP Modular Computers GmbH
2.4.5
Background Debug Mode Interface Connector
The VSBC-32(E) is equipped with a background debug mode (BDM) interface connector
(one 12-pin row male connector). This connector allows an external debugger to be
interfaced to the MC68(EN)360 for controlling purposes. The interface connector is
specified by Motorola.
The pinouts of the BDM interface connector are shown in the following table. For any
further details, please refer to the Motorola MC68(EN)360 User’s Manual.
2.4.6
VMEbus Backplane Interface
The VSBC-32(E) is equipped with a VMEbus backplane interface connector.
The board is provided with a complete master interface for the VMEbus backplane con-
nector. The VMEbus master interface consists of a VMEbus arbiter, requester, system
controller and buffers for data/address/control signals. Simultaneously, the VSBC-32(E)
can act as a VMEbus slave, as it is provided with a slave interface which consists of a
programmable board address decoder, a dual-ported SRAM access and a mailbox
interrupt controller.
To act as a system controller, the VSBC-32(E) is provided with arbiter, system clock
driver, power monitor with system reset driver, IACK daisy chain driver and 7-level
VMEbus interrupt controller.
Arbitration is single-level FAIR (compare VME64 Specification Rule 3.14/Observation
3.17) on BR3*. If the VSBC-32(E) is used as a system controller, a special detection
function provided by the board, which is also readable within the VMEbus control/status
register, makes any “slot 1” jumper setting superfluous. The VMEbus interrupt acknowl-
edgement is controlled via a daisy chain driver that is supplied with the board. IACK* is
connected via the VMEbus backplane for IACKIN* of the system slot.
The signals SYSCLK* and SYSRES* can be routed from on-board to the VMEbus
through the use of jumpers, leaving to the VMEbus user instead of the system controller
the initiative of generating these signals. SYSFAIL* generates a maskable on-board
autovectored level-3 interrupt (please refer also to the section System Control Function-
ality (Interrupt Control) of this chapter), whereas ACFAIL* generates a non-maskable
on-board level-7 interrupt.
Table 2-4: BDM Interface Connector Pinouts
Pin
Signal
Pin
Signal
1
GND
2
CLKO1
3
DS*
4
BERR*
5
GND
6
BKPT* / DSCLK
7
GND
8
FREEZE
9
RESETH*
10
IFETCH / DSI
11
VCC
12
IPIPE0 / DSO
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