CP302
Functional Description and Configuration
ID 21112, Rev. 05
Page 2 - 35
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PEP Modular Computers GmbH
2.9 Special Registers Description
The following registers are special registers for the CP302 to watch the onboard
hardware special features and the CompactPCI control signals.
Normally, only the system BIOS uses these registers, but they are documented here for
application use as required. Take care when modifying the contents of these registers
as the system BIOS may be relying on the state of the bits under its control.
2.9.1
Watchdog
The CP302 has one watchdog timer. This timer is provided with a programmable
timeout ranging from 125 msec to 256 sec. Failure to retrigger the watchdog timer within
a set time period results in a system reset, SMI or an interrupt. These can be configured
via the register 0x284.
To enable the watchdog bit 4 of the register 0x282 must be set. If the watchdog is
enabled via bit 4” this bit cannot later be cleared.
With a write access to the register 0x280 the watchdog is re-triggered. Once the
watchdog is enabled. Once the watchdog is enabled, it must be continuously strobed
within the terminal count period to avoid expiry of the Watchdog..
2.9.1.1 Watchdog Trigger
A write access triggers the watchdog.
The I/O location for the watchdog trigger is 0x280.
Watchdog Timer section appears on the following page
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