Page 6
Pentek Model 78661 Installation Manual
Rev.: 1.7
1.4
Block Diagram
The following is a simplified block diagram of the Model 78661 A/D module.
Figure 1
−
1: Model 78661 Block Diagram
Clock/Sync/
PPS/Gate
TIMING
CONTROL
VCXO
IN 1
RF In
IN 2
RF In
200 MHz
16−BIT A/D
200 MHz
16−BIT A/D
RF
XFORMER
16
16
RF
XFORMER
IN 3
RF In
200 MHz
16−BIT A/D
16
RF
XFORMER
TTL Sync/PPS
TTL Gate/Trig
Sample Clk A
Sample Clk B
Gate A/D
Gate D/A
Sync A/D / PPS
Sync D/A / PPS
Sample Clk /
Reference Clk In
A/D Timing Bus
FLASH
64 MB
GPIO
P14
P15
Model 7806
PCIe Carrier
PCI Express (x8)
SER
I/O B
SER
I/O A
Virtex−6
FPGA
P16
x4
PCIe
16
QDRII+
SRAM
QDRII+
SRAM
16
16
DDR3
SDRAM
DDR3
SDRAM
QDRII+
SRAM
QDRII+
SRAM
16
16
DDR3
SDRAM
DDR3
SDRAM
16
16
16
16
Option 150
Option 155
Memory Banks A/B
Option 160
Option 165
Memory Banks C/D
Aurora
ADC Input Routing
DDC 2
DDC 3
Beamformer
FPGA
I/O
20
pair
PCI Express Interface
ADC 2
Acquisition
Module
ADC 3
Acquisition
Module
DDC 1
ADC 1
Acquisition
Module
x4
IN 4
RF In
200 MHz
16−BIT A/D
16
RF
XFORMER
DDC 4
ADC 4
Acquisition
Module