Pantech PG-1210, Руководство по обслуживанию

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PG-1210 Service Manual
4.2 Radio Transceiver Section
Fig.4-1. RF Transceiver block diagram
The PG-1210’s RF Transceiver, which is Aero II, is the industry's most integrated RF front end for
multi-band GSM/GPRS digital cellular handsets and wireless data modems. The high-level of
integration obtained through patented and proven design architectures, fine line CMOS process
technology, and high-performance quad flat no-lead (QFN) technology results in a transceiver
solution with industry-leading performance, the smallest form factor, the fewest number of
components, the smallest solution footprint, and the lowest bill of materials (BOM) in the industry. A
quad-band RF front end using the Aero II transceiver can be implemented with 19 components in less
than 1 cm
2
of board area. This level of integration is an enabling force in lowering the cost, simplifying
the design and manufacturing, and shrinking the form factor in next-generation GSM/GPRS voice and
data terminals. The receive section uses a digital low-IF architecture that avoids the difficulties
associated with direct conversion while delivering higher performance, lower solution cost, and
reduced complexity. The baseband interface is compatible with any supplier's baseband The transmit
section is a complete up-conversion path from the baseband subsystem to the power amplifier, and
uses an offset phase-locked loop (OPLL) with a The frequency synthesizer uses Silicon Laboratories'
proven technology that includes an integrated RF VCO, loop filter, and varactor. The unique integer-N
PLL architecture produces a transient response superior in speed to fractional-N architectures
without suffering the high phase noise or spurious modulation effects often associated with those
designs. This fast transient response makes the Aero II transceiver well suited to GPRS multi-slot
applications where channel switching The analog baseband interface is used with conventional GSM
baseband ICs (BBIC). The receive and transmit baseband I/Q pins are multiplexed together in a
4-wire interface. A standard three-wire serial interface is used to control the transceiver.
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