Panasonic SJ-MJ50GH, Руководство по обслуживанию

Страница: 49 / 67

Pin
No.
Mark I/O
Division
Function
65 SLD1 I Sled control signal input
terminal
66 SLD2 I Sled control signal input
terminal
67 SLD3 I Sled control signal input
terminal
68 FOPWMF O Focus PMW output terminal
69 FOPWMR O Focus PMW output terminal
70 TRPWMF O Tracking PMW output
terminal
71 TRPWMR O Ttacking PMW output
terminal
72 FG I Verocity puls signal input
terminal
73 VP — CLV servo clock
judgement output terminal
(Not used, open)
74 FOK O Focus OK signal output
terminal
75 FAST — FAST signal output terminal
(Not used, open)
76 VDD I Power supply terminal
77 CL I CPU I/F data transfer clock
input terminal
78 CE I CPU I/F chip enable signal
input terminal
79 DI I CPU I/F data input terminal
80 DO O CPU I/F data output
terminal
81 WRQB O CPU interrupt signal output
terminal
82 INTB O CPU I/F interrupt signal
output terminal
83 FSEQ — Frame synchronize
detection signal output
terminal (Not used, open)
84 F16M O Crystal oscillator output
terminal
(F=16.9344MHz)
85 AVDD — Power supply terminal of
LPF for 1bit DAC
49