Panasonic SJ-MJ50GH, Руководство по обслуживанию

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26 FF2 O F2 signal IV conversion
output terminal
Pin
No.
Mark I/O
Division
Function
27 FF1 O F1 signal IV conversion
output terminal
28 RGND — GND terminal
29 BOTTOM — RF bottom signal output
terminal
(Not used, open)
30 PEAK O RF peak signal output
terminal
31 HFL O Track detection signal
output terminal
32 BHC O Connected to GND through
capacitor
33 PHC O Connected to GND through
capacitor
34 EQO O RF equalizer output
terminal
35 EQI I RF equalizer input terminal
36 RFO O RF signal output terminal
12.2. IC101 (C1BB00000639): ATRAC ENCORDER/
DECORDER, SERVO SIGNAL PROCESSOR
Pin
No.
Mark I/O
Division
Function
1 VDD I Power supply terminal
2 SLCO O HF signal slicing level
output terminal
3 SLCISET I Slicing level adjustment
bias resistor terminal
4 EFMIN I HF signal input terminal
5 TEST1 I Test terminal
6 RESET B I System reset input terminal
7 HFL I Ttack detection signal
input terminal
8 PDO O VCEC current charge pump
output terminal
9 VCVDD I Power supply terminal for
VCEC
10 FR I VCEC oscillation frequency
bias resistor terminal
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