F06S/F06T 2U System Contribution
29
3.17
Debug header Information
3.17.1
XDP Support
Standard XDP header mounted on F06 OCP motherboard for Intel Xeon E5 v3 processors (XDP) will be
depopulated after production.
3.17.2
SMB Debug Header (JP7)
SMB Debug Header is a SMB debug header which is connected to PCH’s HOST channel and BMC SMB channel 4.
Figure 3-6 F06 OCP motherboard SMB debug Header
3.17.3
BMC Debug Header (J1 and J10)
F06 OCP motherboard provides an interface to monitor BMC and host console by debug board, you need to plug
debug board into J1 of motherboard, then press channel SW button to select BMC or Host.
You can disable BMC from J10 for specific usage.
Figure 3-7 F06 OCP motherboard BMC debug header
Figure 3-8 F06 OCP motherboard BMC Disable header
