F06S/F06T 2U System Contribution
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3.8
PCIe BUS
PCI Express* Gen1, Gen2 and Gen 3 are dual-simplex point-to point serial differential low-voltage interconnects.
The signaling bit rate is 2.5 Gbit/s one direction per lane for Gen1 (8b/10b encoding), 5.0 Gb/s one direction per
lane for Gen2 (8b/10b encoding) and 8.0 Gb/s one direction per lane for Gen3 (128b/130b encoding). Each port
consists of a transmitter and receiver pair. A link between the ports of two devices is a collection of lanes (x1, x2,
x4, x8, x16).
3.8.1
PCIe PORT CONNECTIVITY
The following diagram lists the usage of the Intel Xeon E5 v3 and C610 (PCH) PCIe bus segments in F06 2U4N
project.
Figure 3-4 F06 OCP motherboard PCIe connectivity
