F06S/F06T 2U System Contribution
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3.12
LPC BUS
The PCH implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The
PCH LPC bus is used to connect to the BMC and to an optional TPM device.
3.13
TPM
The PCH supports TPM specification 1.2 level2 revisions 103. The F06 OCP motherboard provides an interface
(connector J12), so you can plug TPM module into this interface for security request.
3.14
Serial port
A debug card defined in “
Facebook Server Intel motherboard V3.1” specification
is installed to motherboard
through a debug header(J1) and it provides one UART serial port, two 7‐segment LED displays, one reset button,
and one UART channel selection button. UART interface provides a host console redirection and BMC debug
console. UART channel selection button sends negative pulse to motherboard to select and rotate UART console in
a loop of (host console‐>BMC debug console‐> host console…so on). Default console channel is on host.
3.15
Fans
F06 OCP motherboard supports 2 fans. But system is adopting Fan Board to support 4 dual-rotor fans. The fan
control and fan speed monitor are from BMC chip. BMC will have Fan Tachometer and PWM function. Note that all
fans will operate at the same speed.
3.16
Jumper Definition
Below table is Jumper definition of F06 OCP motherboard.
JUMPER
LOCATION DEFAULT SETTING.
FUNCTION
ME debug header
JP3
Pin1
Pin3
Pin1: Smb_Host_3V3sb_Clk
Pin3: Smb_Host_3V3sb_Dat
ME FIRMWARE
UPDATE
JP4
1-2
1-2 : HOLD (DEFAULT)
2-3 : ME IN FORCE UPDATE MODE
RECOVER BIOS
JUMPER
JP5
1-2
1-2 : HOLD (DEFAULT)
2-3 : RECOVER BIOS
SMB_SML0 debug
header
JP7
Pin1
Pin3
Pin1: Smb_Sml0_3V3sb_Clk
Pin3: Smb_Sml0_3V3sb_Dat
Debug port Voltage
selection
JP1
1-2
1-2 : P5V (DEFAULT)
2-3 : P5V_AUX
CLR RTC_RST
JP10
1-2
1-2 : HOLD (DEFAULT)
2-3 : CLR RTC_RST
VR Debug header
PJP1
Pin1
Pin2
Pin1: SMB_3V3SB_VR12_CLK
Pin2: SMB_3V3SB_VR12_DAT
