44
OSD3358-SM-RED
– User Guide
Rev. 1.0 9/19/2017
Octavo Systems LLC
Copyright 2017
Figure 42
shows the reset circuit in the design schematic. The PMIC’s PGOOD output controls
the PWRONRST input of the processor. So, the processor is held in reset until PMIC_PGOOD
comes up which means all the power rail outputs of the PMIC are up and stable.
Figure 42: OSD3358-SM-RED reset circuit
Figure 42 also shows the reset mechanism for the WARMRSTN input of the processor.
WARMRSTN input is a soft reset and does not affect most of the power/boot systems of the
processor unlike PWRONRSTN. While PMIC_PGOOD and PWRONRSTN operate on 1.8V
logic, WARMRSTN is 3.3V logic input. Therefore, an open drain buffer U3 is used to drive the
WARMRSTN input. WARMRSTN can also be pulled low using the reset switch S1. As the
switch output is susceptible to ground bounce, causing multiple or partial reset, a reset
supervisor U4 is used in between the output of the switch and WARMRSTN input. For more
information on the reset circuit and the functions of each signals, please refer to the ‘OSD335x
Design Tutorial series’ ‘OSD335x Reset Circuitry’ article
(
https://octavosystems.com/app_notes/osd335x-design-tutorial/bare-minimum-boot/reset-
NOTE:
PWRONRSTN holds all the processor systems under reset except for RTC
module. The RTC module has its own power-on-reset input, the RTC_PWRONRSTN pin of
OSD335x.
