UM10741
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© NXP B.V. 2014. All rights reserved.
User manual
Rev. 1 — 1 April 2014
47 of 61
NXP Semiconductors
UM10741
Fm+ development kit OM13320
7.1 Theory
of
operation
Two identical bus buffer devices are connected in series between the Bus1 and Bus2
segments on the Fm+ Development Board (OM13260). Each Bus Buffer has two identical
channels, one for I
2
C clock (SCL) and the second for I
2
C data (SDA). Only one channel
will be described in detail.
Each PCA9617A bus buffer device has two power supply connections, V
CC(A)
and V
CC(B)
,
to allow voltage level shifting between one I
2
C-bus segment and another I
2
C-bus
segment. Jumpers on the Bus Buffer Board (OM13398) select the voltage source of each
of the two device power supplies. To demonstrate the voltage level translator ability the
link between the two bus buffers is supplied from a variable voltage regulator, which in
turn can be set by the user anywhere between 1.0 V and 3.2 V.
The pull-up resistor on the Low Voltage Bus section is selected by jumpers.
7.2 Circuit
description
The schematic diagram has multiple sheets. For clarification, only fragments of the
schematic are shown here. The full schematic should be downloaded if required. The
following pages are divided in to several sections covering the Bus1 Bus Buffer, Bus2 Bus
Buffer, Supply select jumpers, Adjustable Voltage Regulator, and Connectors. A block
diagram will assist understanding. See
Figure 66
.
Fig 66. Block diagram for the bus buffer board (OM13398)
aaa-012142
3.3 V
PULL-UP
RESISTORS
ADJUSTABLE
VOLTAGE
REGULATOR
1.0 V to 3.2 V
JP2
V
CC(A)
5 V
V
CC(A)
3.3 V
JP1
V
CC(B)
5 V
PCA9617A
BUS1
B
A
PCA9617A
A
B
BUS2
V
CC(B)
V
CC(A)
V
CC(A)
V
CC(B)
low
voltage
bus
