TWR-56F8400 User’s Manual
Page 17 of 35
on prototypes of the TWR56F8400. Leaving the shunt on the header enables the OSBDM/OSJTAG
debug interface. Removing the shunt on header J20 enables the USB Serial Bridge interface. The
header, J20, is subsequently reserved for future use.
2.4.5
Bootloader Enable
In addition to the OSBDM/OSJTAG Debug interface and the USB Serial Bridge interface the
MC9S08JM60 device used in the OSBDM/OSJTAG circuit is preprogrammed with a USB Bootloader.
The USB Bootloader will run following a power-on reset if a shunt is installed on header J17. This
allows in-circuit reprogramming of the JM60 flash memory via USB. This enables the OSBDM/OSJTAG
firmware to be upgraded by the user when upgrades become available. In normal OSBDM/OSJTAG /
USB Serial Bridge operation this shunt must be left off. For details on the USB Bootloader, refer
to
Application Note AN3561
on the Freescale website (
http://www.freescale.com
The USB Bootloader communicates with a GUI application running on a host PC. The GUI application
can be found on the
Freescale website
; search keyword “JM60 GUI”. Refer to section 2.5 and 3.3 of
AN3561 for details on installing and running the application.
2.4.6
BDM Header
The BDM header at J22 is used for initial programming of the MC9S08JM60 MCU or if reprogramming
when the bootloader fails. An external 9S08 BDM debugger would be connected to J22 and used to
program the MCU. This is not expected to be a normal user interface, however it is useful if the ‘JM60
device is inadvertently reprogrammed with firmware that is not functional.
2.4.7
OSBDM/OSJTAG Status LEDs
The MC9S08JM60 OSBDM/OSJTAG MCU controls two status LEDs at D12 and D13. Refer to the
OSBDM/OSJTAG instructions for the meaning of the LEDs.
2.4.8
OSBDM/OSJTAG Voltage Translation
Since the OSBDM/OSJTAG MCU runs from 5V and the 56F84789 DSC runs from 3.3V there needs to be
voltage translation between the two circuits. This is done through U505, U504A and U502B. U505 has
5V tolerant inputs and provides 3.3V signals (TCK, TDI, and TMS) to the DSC’s JTAG pins through the
shunts on header J21. U504A is powered by the P3_3V/5V rail and translates the 3.3V TDO signal from
the DSC to a 5V signal for the OSBDM/OSJTAG MCU. The outputs of both of these translators are high
impedance if the signal OUT_EN_B goes high. This happens if the OSBDM/OSJTAG circuit looses power
(no power to the USB connector). In that case the OUT_EN signal from the OSBDM/OSJTAG MCU (pin
15) is biased low by R12. The inverter at U502B then drives OUT_EN_B high in response. Additional
information is included in section 2.4.2.
