TWR-56F8400 User’s Manual
Page 15 of 35
pin 3. A 120 ohm parallel termination resistor,R560, may be connected between these nets by
installing a shunt on header J15.
2.3.9
IRQ or Input Pushbuttons
The TWR-56F8400 board has two pushbuttons (SW1 and SW2) that can be used to provide inputs or
interrupts to the DSC. Each has a 10K ohm pull up resistor to P3_3V and a 0.1 uF capacitor to ground to
minimize bounce on the output.
Pushbutton SW1 is connected to header J4 where the switch output can be connected to either DSC
pin GPIOC2/TXD0/TB0/XB_IN2/CLKO0 (default) or GPIOF6/TB2/PWMA_3X/PWMB_3X/XB_IN2
depending on the position of the shunt on the header (pin 1 to pin 2 is the default). Similarly,
pushbutton SW2 is connected to header J5 where the switch output can be connected to either DSC
pin GPIOF8/RXD0/TB1/CMPD_O (default) or GPIOF7/TB3/CMPC_O/SS1_B/XB_IN3 depending on the
position of the shunt on the header (pin 1 to pin 2 is the default).
If the pushbutton switches are not being used as an interrupt, or other purpose, it is best to remove
the shunt to the DSC so that the 0.1 uF capacitor is not loading down the DSC pins.
2.3.10
RESET
The GPIOD4/RESET_B pin of the DSC is connected to the motor control connector and the tower
connector but also to a pushbutton (SW3) and through buffers to the OSBDM/OSJTAG chip. It is pulled
to P3_3V by a 10K ohm resistor. It may be pulled low by the pushbutton or by Q1 in response to a high
output from the OSBDM/OSJTAG chip (pin 1) on the TRESET_OUT net. The state of the
GPIOD4/RESET_B signal is provided to the OSBDM/OSJTAG chip through a voltage translator (U504B).
This buffer is powered by the P3_3V/5V power rail so that its input will remain high impedance when
there is no USB cable connected. The buffered RESET signal is provided to pin 33 of the
OSBDM/OSJTAG chip and is used by the OSBDM/OSJTAG program in that chip.
2.3.11
JTAG Header and OSBDM/OSJTAG Disconnect Header
The TWR-56F8400 board includes an OSBDM/OSJTAG circuit as a debug interface to the MC56F84789
DSC for normal purposes. If the user desires to use a different debugger connection, header J14
provides a connection point for an external JTAG aware debugger. If an external debugger is connected
to the JTAG header the shunts at J21 (pins 1 to 2, 3 to 4, 5 to 6, and 7 to 8) which connect the
OSBDM/OSJTAG circuit to the JTAG signals should be removed, allowing the external debugger to
control the JTAG port, rather than the ‘JM60.
The TWR-56F8400 board provides a 2.2K ohm pull up resistor to 3.3V on the TMS line. If an external
JTAG aware debugger also has a pull up on this line, the external debugger may not be able to pull the
TMS line low. If this happens, remove one of the pull up resistors on the TMS line.
