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4/2022
NXP Semiconductors
UM11401
FRDMGD31RPEVM half-bridge evaluation board
Figure 3. Evaluation board voltage and interface domains
Pin
Name
Function
1
AOUTL
analog output duty cycle encoded signal (low side) for reading temperature via
TSENSEA or voltage via AMUXIN
2
n.c.
not connected
3
CSBL
chip select bar (low side)
4
n.c.
not connected
5
PWML
pulse width modulation (PWM) input (low side)
6
INTBL
interrupt bar (low side)
7
MOSIL
master out slave in (low side)
8
SCLK
serial clock input
9
MISOL
master in slave out (low side)
10
n.c.
not connected
11
FSSTATEL
fail-safe state (low side)
12
GND
ground
13
FSENB
fail-safe enable (high side and low side)
14
MISOH
master in slave out (high side)
Table 2. Low-voltage domain 24-pin connector definitions
UM11401
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© NXP B.V. 2021. All rights reserved.
User guide
Rev. 2 — 22 January 2021
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