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The onboard Ethernet PHYs, Realtek RTL8211FS (U16 and U17), are connected to the
LS1012A processor EC1 and EC2 using the SGMII protocol over SerDes lane A and
SerDes lane B.

MDIO

MDC

Ethernet Controller

LS1012

3V3

3V3

3V3_RST_B

SGMII

MDI_0_P/N

MDI_1_P/N

MDI_3_P/N

MDI_2_P/N

PMEB

INTB

PHYRSTB

DVDD_RG

DVDD33

4.7K

PHY

SUPPORT 

MODE: SGMII

RJ-45 

1Gbps

100Mbps

3V3

4.7K

1V

REG_OUT

AVDD10

DVDD10

AVDD33

0 ohm

#1

REALTEK RTL8211FS-CG

48-PIN QFN

Notes and Assumptions:

- MAC connected to Serdes lane B is the same MAC connected to the RGMII interface. 

so RGMII and SGMII ( lane B) can not be use at a time.

- If the Serdes is configured for 2 SGMII interfaces, then the RGMII interface is unused 

(tristated unless the pinmuxing control register is configured for functionality other than 
EC1 RGMII).

S

E

R

D

E

S

L

a

n

e A

TX_P/N

RX_P/N

HSIP/N

HSOP/N

EM1_MDC

EM1_MDIO

X

Transfo rmer

O

V

D

D

1.8

V

Voltage

Translator

1.8V 3.3V

VSEL/

GPIO_1[13]

Figure 2-5. SGMII PHY1

Chapter 2 LS1012AFRDM Functional Description

QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016

NXP Semiconductors

19

Содержание QorIQ FRDM-LS1012A

Страница 1: ...QorIQ FRDM LS1012A Board Reference Manual Document Number FRDM LS1012ARM Rev 3 12 2016...

Страница 2: ...QorIQ FRDM LS1012A Board Reference Manual Rev 3 12 2016 2 NXP Semiconductors...

Страница 3: ...rimary power supply 12 2 2 2 FRDM LS1012A power supply delivery system 13 2 2 3 Power ON 14 2 2 4 Voltage regulation 14 2 3 Reset and configuration signals 15 2 4 Clocks 17 2 5 Double data rate DDR me...

Страница 4: ...2 13 Ardiuno 24 2 14 JTAG port 24 2 14 1 CMSIS DAP 24 2 15 GPIO pins 25 2 16 Temperature 26 2 17 Power monitoring LEDs 26 2 18 Revision control 26 QorIQ FRDM LS1012A Board Reference Manual Rev 3 12 2...

Страница 5: ...nd the general purpose embedded applications The FRDM LS1012A onboard resources and debugging devices allow you to Upload and run code Use the FRDM LS1012A as a demonstration tool A software applicati...

Страница 6: ...mendations for new designs based on LS1012A This document can also be used to debug newly designed systems by highlighting those aspects of a design that merit special attention during initial system...

Страница 7: ...connector USB 2 0 port is a debug port CMSIS DAP and is configured as a Micro AB device SPI SPI SC16IS740IPW SPI to Dual UART bridge Arduino QSPI One QSPI controller Onboard 64 MB QSPI flash memory ru...

Страница 8: ...DD 3 3 G1VDD 1 35V XVDD 1 35V AVDD_CGA PLAT 1 8V AVDD_SD1 2_PLL1 2 1 35V USB_SVDD SDVDD 0 9V 3V3 Board supply 2 3 1 3 1 2 1 2 1 2 SGMII 1G USB3 x2 USB2 0 USB3 0 QSPI NOR FLASH S25FL128SAGMFIR0 OVDD 1...

Страница 9: ...9 Header for USB power J12 K20 JTAG header J10 Reset switch SW1 USB 2 0 debug UART connector J11 SGMII PHY2 J7 ETH2 SGMII PHY1 J6 ETH1 SDA_LED D1 USB VBUS LED D2 PORST LED D3 Figure 1 2 FRDM LS1012A t...

Страница 10: ...FRDM LS1012A top view QorIQ FRDM LS1012A Board Reference Manual Rev 3 12 2016 10 NXP Semiconductors...

Страница 11: ...networking wireless infrastructure and general purpose embedded applications NOTE For details about features of the LS1012A processor see QorIQ LS1012A Family Reference Manual 2 2 Power supplies The F...

Страница 12: ...5A max VDD_Core 1 35V LDO2 0 250 max Unused 1 55V LDO1 0 1A max 0V 1 89V LDO4 0 350A V33 0 35A max LDO3 0 1A 1 8V 3 3V 9A SEPIC USB1 3 0 PORESET_B 5V MAX8586 US B 1_DRVVB US LPF AVDD_CGA1 V18 0 1A 1...

Страница 13: ...apacity from host and provide required power to the FRDM LS1012A NOTE The Power estimation list does not show the power taken by the external devices such as USB 3 0 device Ardiuno cards 2 2 2 FRDM LS...

Страница 14: ...es Table 2 2 describes the Power ON sequence as implemented on the FRDM LS1012A Table 2 2 Power ON process Step Indication Specifics Description 1 5V Power supply provided by USB2 0 Micro AB port Acts...

Страница 15: ...SW1 TH_VDD 1 8 V 1 25 A max VR5100 SW2 Thermal monitor unit supply voltage AVDD_CGA1 AVDD_PLAT Core Platform DDR and SerDes PLL s supply voltages XOSC_VDD OVDD supply for LS1012A crystal oscillator OV...

Страница 16: ...ipherals Enables the BOOTLOADER mode on the K20 CMSISDAP Debugger reset J9 and K20 Reset from JTAG debugger No power cycle All devices are reset RESET_REQ_B Reset request from LS1012A All devices are...

Страница 17: ...ce EXTAL Bypass mode 25 MHz Input clock for SoC ETH1_REFCLK 25 MHz Reference clock for the SGMII PHY1 Oscillator KC2520C25 0000C1LE00 and clock buffer 524S Additive phase jitter RMS 50 fs Skew outputs...

Страница 18: ...ry bus 2 6 Serializer deserializer SerDes The FRDM LS1012A SerDes block provides two high speed serial communication lane supporting SGMII PHYs See QorIQ LS1012A Data Sheet for details about the SerDe...

Страница 19: ...8 PIN QFN Notes and Assumptions MAC connected to Serdes lane B is the same MAC connected to the RGMII interface so RGMII and SGMII lane B can not be use at a time If the Serdes is configured for 2 SGM...

Страница 20: ...aces then the RGMII interface is unused tristated unless the pinmuxing control register is configured for functionality other than EC1 RGMII SERDES Lane B TX_P N RX_P N HSIP N HSOP N EM1_MDC EM1_MDIO...

Страница 21: ...0 generates these clocks based on a 25 MHz MCLK which is fed from the CLKOUT of LS1012A The SGTL5000 control interface is I2C based and can be accessed at the 0x0A address 2 9 USB interface The FRDM L...

Страница 22: ...bug port J11 to turn on the board 2 10 I2C ports The FRDM LS1012A support one I2C bus The LS1012A I2C1 is attached to the local devices on the FRDM LS1012A The level shifter device NTSX2102GU8H is use...

Страница 23: ...RDM LS1012A supports QSPI as the primary system boot source The FRDM LS1012A supports onboard Spansion S25FS512SAGNFI011 quad SPI serial flash memory with 64 MB space LS1012A supports only one QSPI co...

Страница 24: ...A consists of the LS1012A SoC and the K20 microcontroller each of which have dedicated debug connectors J9 and J10 can be used by external debuggers such as CWTAP DSTREAM to debug LS1012A and K20 resp...

Страница 25: ...ug interfaces serial to USB converters and so on 2 15 GPIO pins LS1012A has no dedicated GPIO pins instead the FRDM LS1012A provides GPIOs through Ardiuno shield Table 2 11 FRDM LS1012A GPIO mapping P...

Страница 26: ...reset monitoring which inform the user about the status of different power rails resets and board faults The FRDM LS1012A LEDs are listed in the following table Table 2 12 FRDM LS1012A LEDs LED legen...

Страница 27: ...2A top side view FRDM LS1012A bottom side view A 1 FRDM LS1012A top side view NOTE For a clear view of the board top side view please zoom in on the Figure Figure A 1 FRDM LS1012A top side view QorIQ...

Страница 28: ...w NOTE For a clear view of the board bottom side view please zoom in on the Figure Figure A 2 FRDM LS1012A bottom side view FRDM LS1012A bottom side view QorIQ FRDM LS1012A Board Reference Manual Rev...

Страница 29: ...Updated top view for Rev c board FRDM LS1012A block diagram Updated FRDM LS1012A block diagram for the Rev C board Voltage regulation Updated Table 2 3 to add VCC_POVDD Clocks In Table 2 6 updated 25M...

Страница 30: ...QorIQ FRDM LS1012A Board Reference Manual Rev 3 12 2016 30 NXP Semiconductors...

Страница 31: ...sequential or incidental damages Typical parameters that may be provided in NXP data sheets and or specifications can and do vary in different applications and actual performance may vary over time Al...

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