NXP Semiconductors QorIQ FRDM-LS1012A, Справочное руководство, Страница: 17 / 31

2.4 Clocks
The architecture of the FRDM-LS1012A clocks is shown in the following figure.
LS1012
EXTAL
ETH SGMII
PHY
RTL8211FS-CG
ETH SGMII
PHY
RTL8211FS-CG
8 MHz
Crystal
K20
Audio
SGTL5000
25MHz
25MHz
SPI to UART
Bridge
SC16IS740IPW
XO
24MHz
24MHz
1:4
CLK
BUFER
25MHz
XO
25MHz
Figure 2-4. Clock architecture
The following table summarizes the FRDM-LS1012A clock distribution.
Table 2-6. FRDM-LS1012A clocks
Clock Frequency Destination Device
EXTAL (Bypass mode) 25 MHz Input clock for SoC
ETH1_REFCLK 25 MHz Reference clock for the
SGMII PHY1 Oscillator (KC2520C25.0000C1LE00) and
clock buffer, 524S:
• Additive phase jitter RMS = 50 fs
• Skew outputs = 50 ps
• Low cost clock buffer
• Input/Output clock frequency up to
200 MHz
ETH2_REFCLK 25 MHz Reference clock for the
SGMII PHY2
CODEC_SYS_MCLK 25 MHz System clock for audio
codec
8MHz XTAL for K20 8 MHz Crystal clock for K20 Crystal
BRDG_CLKIN_24MHz 24 MHz Clock for SC16IS740IPW
SPI to Dual UART bridge Oscillator
Chapter 2 LS1012AFRDM Functional Description
QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016
NXP Semiconductors 17