NXP Semiconductors
UM191812
PN544 C2 User Manual
191812
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
User Manual
Rev. 1.2 — 2010-06-16
137 of 172
Both the host and the UICC must configure their pipes as defined in HCI specification.
The host must in addition set some NXP proprietary parameters to enable the UICC as a
reader (refer to SWP paragraph). The next figure shows those exchanges between the
host, the PN544 and the UICC.
HOST
PN544
mandatory
optional
EVT_READER_REQUESTED*
* This activates all reader types whose gate is opened
Type A RF
Reader Gate
Type A
Reader Gate
UICC
Type A
Reader Gate
EVT_READER_REQUESTED*
* This activates all reader types whose gate is opened
Type A RF
Reader Gate
NXP_SWP_DEFAULTMODE
to enable SWP link
NXP_READ/WRITE (
SwpMgt_Request_Power
)
to choose the pin used to request power
NXP_READ/WRITE (
SWP_Bitrate
)
to change the baudrate on SWP
NXP_SWP_RIGHTS_RD
to allow UICC type A reader mode
NXP_SWP_STATUS
to check the presence of a SWP UICC
SWP gate
NXP_EVENT_ACTIVATE_RD_PHASES
to allow Type A reader
PL Gate
(Polling
Loop gate)
NXP_PL_RDPHASES
to allow Reader type A
The NXP_PL_RD_PHASES can be placed
before the EVT_READER_REQUESTED
If NXP_PL_RDPHASES type A would not have been
sent before, it would be send here.
PL Gate
(Polling
Loop gate)
Create/open
pipes are not
shown here
SWP gate
STATIC**
DYNAMIC
**to be performed
one time
PL Gate
(Polling
Loop gate)
PL Gate
(Polling
Loop gate)
System
gate
System
gate
Fig 72. Initialization of PN544
The next figure shows what happen when a card is present in the external field.
The host is the first to receive the information that a card is present in the RF field. The
UICC will be able to communicate with the card only after the host has sent
NXP_WR_DISPATCH_TO_UICC
.