UM10539
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
5 of 7
NXP Semiconductors
UM10539
NVT2003DP, NVT2004TL and NVT2006PW demo boards
2.2 Jumper and header functions
The functions of the jumpers and headers on this demo board are shown in
Table 1
.
3. Abbreviations
4. References
[1]
NVT2003/04/06, “Bidirectional voltage-level translator for open-drain and
push-pull applications” —
Product data sheet; NXP Semiconductors;
www.nxp.com/documents/data_sheet/NVT2003_04_06.pdf
[2]
AN11127, “Bidirectional voltage level translators NVT20xx, PCA9306,
GTL2000, GTL2002, GTL2003, GTL2010” —
application note;
NXP Semiconductors;
www.nxp.com/documents/application_note/AN11127.pdf
Table 1.
Header descriptions for NVT2003DP (OM13319), NVT2004TL (OM13316) or NVT2006PW (OM13323)
demo boards
Jumper/header
Function
Notes
J1 (3-pin)
Device switch enable or disable
control
Short pins 2 and 3 to enable the NVT2003DP, NVT2004TL or
NVT2006PW device (default). When pins 1 and 2 are shorted,
the device is disabled.
J2 (2-pin)
Connects 10 k
Ω
pull-up resistors to
VREFA on low voltage side for
VREFB
−
VREFA < 1 V
Short pins 1 and 2 to connect 10 k
Ω
pull-up resistors to VREFA
on low voltage side.
Remark:
Pins 1 and 2 must be open and 10 k
Ω
pull-up resistors
must be removed when VREFB
−
VREFA
≥
1 V.
J3 (8-pin)
Low voltage VREFA, GND and
An I/O signal connect pins
Pin 1 = VREFA: low voltage power.
Pin 8 = GND: low voltage ground.
A[1:3] are low voltage signals for NVT2003DP.
A[1:4] are low voltage signals for NVT2004TL.
A[1:6] are low voltage signals for NVT2006PW.
J4 (8-pin)
High voltage VREFB, GND and
Bn I/O signal connect pins
Pin 1 = VREFB: high voltage power.
Pin 8 = GND: high voltage ground.
B[1:3] are high voltage signals for NVT2003DP.
B[1:4] are high voltage signals for NVT2004TL.
B[1:6] are high voltage signals for NVT2006PW.
Table 2.
Abbreviations
Acronym
Description
I
2
C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
SPI
Serial Peripheral Interface
SMBus
System Management Bus
