UM10539
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1 — 7 March 2012
4 of 7
NXP Semiconductors
UM10539
NVT2003DP, NVT2004TL and NVT2006PW demo boards
2. Hardware
description
2.1 Schematic
The demo boards contain footprints for the NVT2003DP, NVT2004TL and NVT2006PW,
where the jumpers, headers, and passive components are shared. The NVT2003DP,
NVT2004TL and NVT2006PW demo board schematic is shown in
Figure 2
. Pin 2 and
pin 3 on J1 need to be shorted to enable the part. Pin 1 and pin 8 on J3 are power and
GND for the low voltage side. Pin 1 and pin 8 on J4 are power and GND for the high
voltage side. All Bn I/O pins on the right side have 10 k
Ω
pull-up resistors to VREFB and
all An I/O pins on the left side have 10 k
Ω
pull-up resistors to VREFA through jumper J2.
A shunt needs to be installed at J2 if VREFB
−
VREFA < 1 V. If VREFB
−
VREFA
≥
1 V,
then the J2 should be open and resistors R2 through R7 must be removed. If they are
not removed, then a resistive path exists between the A-side I/Os that can impact the
efficiency and signal integrity of the solution.
Fig 2.
NVT2003DP, NVT2004TL and NVT2006PW demo board schematic
002aag939
EN
VREFB
B1
B2
B3
B4
B5
B6
16
15
14
13
12
11
9
10
VREFA
A1
A2
A3
A4
A5
A6
2
3
4
5
6
8
7
GND
1
NVT2006PW
0.1 μF
R7
10 kΩ
R6
10 kΩ
R5
10 kΩ
R4
10 kΩ
R3
10 kΩ
R2
10 kΩ
U1
A2
A3
A4
A5
A6
GND
3
4
5
6
8
7
A1
2
VREFA
1
low voltage
A-side
J3
CON8
21
J2
JP
Jumper:
ON: if VREFB − VREFA < 1 V
(populated 10 kΩ pull-up resistors)
OFF: if VREFB − VREFA ≥ 1 V
(do not populate 10 kΩ pull-up resistors)
EN_VREFB
R1
200 kΩ
C1
R13
10 kΩ
R12
10 kΩ
R1
1
10 kΩ
R10
10 kΩ
R9
10 kΩ
R8
10 kΩ
B2
B3
B4
B5
B6
GND
3
4
5
6
8
7
B1
2
VREFB
1
J4
CON8
high voltage
B-side
2
3
1
J1
2-3: switch enable
1-2: switch disable
EN
VREFB
B1
B2
B3
B4
12
11
10
9
8
7
VREFA
A1
A2
A3
A4
2
3
4
5
6
GND
1
NVT2004TL
U2
EN_VREFB
EN
VREFB
B1
B2
B3
10
9
8
7
6
VREFA
A1
A2
A3
2
3
4
5
GND
1
NVT2003DP
U3
EN_VREFB
