NXP Semiconductors MKW01Z128, Справочное руководство

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Transceiver Digital Control and Communications
MKW01xxRM Reference Manual, Rev. 3, 04/2016
7-14 Freescale Semiconductor, Inc.
7.5.5 AES
AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The
system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only
user configuration register, which retains its value in Sleep mode.
As shown in Figure 7-10 and Figure 7-11 above the message part of the Packet can be encrypted and
decrypted with the cipher 128- cipher key stored in the configuration registers.
7.5.5.1 TX Processing
1. User enters the data to be transmitted in FIFO in Stdby/Sleep mode and gives the transmit
command.
2. On TX command the Packet handler state machine takes over the control and If encryption is
enabled then the message inside the FIFO is read in blocks of 16 bytes (padded with 0s if needed),
encrypted and stored back to FIFO. All this processing is done in TX mode before enabling the
packet handling state machine. Only the Message part of the packet is encrypted and preamble,
sync word, length byte, address byte and CRC are not encrypted.
3. Once the encryption is done the Packet handling state machine is enabled to transmit the data.
7.5.5.2 RX Processing
1. The data received is stored in the FIFO, The address, CRC interrupts are generated as usual because
these parameters were not encrypted.
2. Once the complete packet has been received. The data is read from the FIFO, decrypted and written
back to FIFO. The PayloadReady interrupt is issued once the decrypted data is ready in the FIFO
for reading via the SPI interface.
The AES encryption/decryption cannot be used on the fly i.e. while transmitting and receiving data. Thus
when AES encryption/decryption is enabled, the FIFO acts as a simple buffer. This buffer is filled before
initiating any transmission. The data in the buffer is then encrypted before the transmission can begin. On
the receive side the decryption is initiated only once the complete packet has been received in the buffer.
The encryption/decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of
4 blocks (i.e. 64 bytes) it can take up to 28 us for completing the cryptographic operations.
The receive side sees the AES decryption time as a sequential delay before the PayloadReady interrupt is
available.
The TX side sees the AES encryption time as a sequential delay in the startup of the TX chain, thus the
startup time of the TX will increase according to the length of data.
In Fixed length mode the Message part of the payload that can be encrypted/decrypted can be 64 bytes
long. If the address filtering is enabled, the length of the payload should be at max 65 bytes in this case.
In Variable length mode the Max message size that can be encrypted/decrypted is also 64 bytes when
address filtering is disabled, else it is 48 bytes. Thus, including length byte, the length of the payload is
max 65 or 50 bytes (the latter when address filtering is enabled).