64 KByte Flash Module (S12XFTMR64K1V1)
S12XS Family Reference Manual, Rev. 1.13
656
Freescale Semiconductor
•
Reset the MCU into special expanded wide mode, disable protection in the P-Flash and D-Flash
memory and run code from external memory to execute the Erase All Blocks command write
sequence to erase the P-Flash and D-Flash memory.
After the CCIF flag sets to indicate that the Erase All Blocks operation has completed, reset the MCU into
special single chip mode. The BDM will execute the Erase Verify All Blocks command write sequence to
verify that the P-Flash and D-Flash memory is erased. If the P-Flash and D-Flash memory are verified as
erased the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may
be programmed to the unsecure state by the following method:
•
Send BDM commands to execute a ‘Program P-Flash’ command sequence to program the Flash
security byte to the unsecured state and reset the MCU.
20.5.3
Mode and Security Effects on Flash Command Availability
The availability of Flash module commands depends on the MCU operating mode and security state as
shown in
20.6
Initialization
On each system reset the Flash module executes a reset sequence which establishes initial values for the
Flash Block Configuration Parameters, the FPROT and DFPROT protection registers, and the FOPT and
FSEC registers. The Flash module reverts to built-in default values that leave the module in a fully
protected and secured state if errors are encountered during execution of the reset sequence. If a double bit
fault is detected during the reset sequence, both MGSTAT bits in the FSTAT register will be set.
CCIF remains clear throughout the reset sequence. The Flash module holds off all CPU access for the
initial portion of the reset sequence. While Flash reads are possible when the hold is removed, writes to
the FCCOBIX, FCCOBHI, and FCCOBLO registers are ignored to prevent command activity while the
Memory Controller remains busy. Completion of the reset sequence is marked by setting CCIF high which
enables writes to the FCCOBIX, FCCOBHI, and FCCOBLO registers to launch any available Flash
command.
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
Содержание MC9S12XS128
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Страница 58: ...Device Overview S12XS Family S12XS Family Reference Manual Rev 1 13 58 Freescale Semiconductor ...
Страница 150: ...Memory Mapping Control S12XMMCV4 S12XS Family Reference Manual Rev 1 13 150 Freescale Semiconductor ...
Страница 168: ...Interrupt S12XINTV2 S12XS Family Reference Manual Rev 1 13 168 Freescale Semiconductor ...
Страница 194: ...Background Debug Module S12XBDMV2 S12XS Family Reference Manual Rev 1 13 194 Freescale Semiconductor ...
Страница 364: ...Periodic Interrupt Timer S12PIT24B4CV1 S12XS Family Reference Manual Rev 1 13 364 Freescale Semiconductor ...
Страница 396: ...Pulse Width Modulator S12PWM8B8CV1 S12XS Family Reference Manual Rev 1 13 396 Freescale Semiconductor ...
Страница 506: ...Voltage Regulator S12VREGL3V3V1 S12XS Family Reference Manual Rev 1 13 506 Freescale Semiconductor ...
Страница 736: ...Ordering Information S12XS Family Reference Manual Rev 1 13 736 Freescale Semiconductor ...
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