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MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor C-1
Appendix C
Prescaler for Jitter Measurement
C.1 Divide-by- xx Prescaler Description
Evaluating jitter in a system requires that all clocks within the system be based on one common source.
For this reason, it is often necessary to use prescalers to derive the needed reference clock. Freescale has
developed a small programmable prescaler with a maximum input frequency of 4.4 GHz which can be
assembled using commercially available parts.
Figure C-1 depicts the block diagram of this prescaler.
Figure C-1. Divide-by- xx Prescaler Block Diagram
The input to the prescaler can be either through a divide-by-2 or directly into the 5-bit programmable
counter. The bank 1 and bank 2 DIP switches can be used to select a variety of prescaler values based on
the following formula:
where A = 1 to 31 and N = 2, 4, or 8.
For values commonly used in 1.0-Gbit systems refer to Table C-1 .
Schematics for this prescaler are available from your Freescale field applications engineer.
Table C-1. Switch Settings for 1.0-Gbit SERDES Prescalers
Input
Bank 1 Bank 2
Modulus
SW5 SW4 SW3 SW2 SW1 SW2 SW1
Clock In_alt 0 0 1 0 0 1 1 5
×
2 = 10
Clock In 0 0 1 0 0 1 1 2
×
5
×
2 = 20
Clock In 0 0 1 0 0 0 1 2
×
5
×
4 = 40
Clock In 0 1 0 0 1 1 1 2
×
10
×
2 = 40
Divide
by 2
Bank 1 Switch
2, 4, or 8
Divide by
Prescaler
5-Bit
Programmable
Counter
Bank 2 Switch
Level
Shift
Clock
Out
Clock
In
Clock
In_alt
Modulus 2 A 1
+
( )
N
⋅ ⋅
=