NXP Semiconductors MC92602, Руководство пользователя, Страница: 22 / 48

Laboratory Equipment and Quick Setup Evaluation
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
3-4 Freescale Semiconductor
3.2.1.2 Parallel Input Connections
The basic eye diagram will be generated by biasing the parallel inputs according to Table 3-4 . Ground
connections can be made using the 0.100" shunts. Connections to +1.5 V V
DDQ
can be made using the
square pin receptacle patch cords and jumpering to the odd numbered pins of headers PG12 and PG14. All
even number pins on the connector headers are connected to the board’s ground plane. All unlisted pins
are not connected.
Table 3-4. Data-Eye Generation Parallel Input Biasing
Connector Pin Signal
Bias
Level
Connector Pin Signal
Bias
Level
TEST_0 9 TDI GND A_XMIT0 1 XMIT_A_0 GND
11 TCK GND 3 XMIT_A_1 GND
13 TMS GND 5 XMIT_A_2 GND
15 TRST GND 7 XMIT_A_3 GND
CTRL_SIG_0 1 REPE GND 9 XMIT_A_K +1.5 V
3 RCCE +1.5 V 11 XCVR_A_DISABLE GND
5 WSE GND A_XCLK 15 XMIT_A_CLK GND
7 HSE GND B_XMIT0 1 XMIT_B_0 GND
9 ADIE GND 3 XMIT_B_1 GND
11 RESET GND 5 XMIT_B_2 GND
15 STNDBY GND 7 XMIT_B_3 GND
CTRL_SIG_1 1 LBOE GND 9 XMIT_B_K +1.5 V
3 LBE GND 11 XCVR_B_DISABLE GND
5 MEDIA GND B_XCLK 15 XMIT_B_CLK GND
7 TBIE GND C_XMIT0 1 XMIT_C_0 GND
9 COMPAT GND 3 XMIT_C_1 GND
13 RECV_REF_A +1.5 V 5 XMIT_C_2 GND
15 XMIT_REF_A +1.5 V 7 XMIT_C_3 GND
CTRL_SIG_2 1 BSYNC +1.5 V 9 XMIT_C_K +1.5 V
3 DROP_SYNC GND 11 XCVR_C_DISABLE GND
5 TST_1 GND C_XCLK 15 XMIT_C_CLK GND
7 TST_0 +1.5 V D_XMIT0 1 XMIT_D_0 GND
3 XMIT_D_1 GND
5 XMIT_D_2 GND
7 XMIT_D_3 GND
9 XMIT_D_K +1.5 V
11 XCVR_D_DISABLE GND
D_XCLK 15 XMITD_CLK GND