NXP Semiconductors KITVR5510 A0EVM Series, Руководство пользователя, Страница: 31 / 32

NXP Semiconductors
UM11587
KITVR5510xA0EVM Evaluation Kit User Guideline
Figures
Fig. 1. LEDs, switches, and the PMIC ......................... 7
Fig. 2. Connectors ........................................................ 8
Fig. 3. Jumpers .............................................................9
Fig. 4. Test points .......................................................11
Fig. 5. KITVR5510xA0EVM layout – top .................... 12
Fig. 6. KITVR5510xA0EVM layout – layer 2 .............. 12
Fig. 7. KITVR5510xA0EVM layout – layer 3 .............. 13
Fig. 8. VR551-xA0EVM layout – layer 4 .....................13
Fig. 9. KITVR5510xA0EVM layout – layer 5 .............. 14
Fig. 10. KITVR5510xA0EVM layout – layer 6 .............. 14
Fig. 11. KITVR5510xA0EVM layout – layer 7 .............. 15
Fig. 12. KITVR5510xA0EVM layout – bottom .............. 15
Fig. 13. Freedom board ................................................19
Fig. 14. Connecting to a reference board with K82F
only ..................................................................22
Fig. 15. NXP GUI - OTP configuration tool - TBB
creation ............................................................23
Fig. 16. Reading FS_STATES [0x18] register from
safety section (0x21h) .....................................24
Fig. 17. Selecting test-mode option ..............................24
Fig. 18. M_TM_STATUS1 (0x25) ................................. 25
Fig. 19. FS_STATES (0x18) ......................................... 25
Fig. 20. Selecting the config source as “script” ............ 26
Fig. 21. Fuse box status ...............................................26
UM11587 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 3 May 2021
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