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Table 58-3. 4-bit JTAG instructions (continued)

Instruction

Code[3:0]

Instruction Summary

ARM JTAG-DP Reserved

1011

This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.

CLAMP

1100

Selects bypass register while applying preloaded values to
output pins and asserting functional reset

ARM JTAG-DP Reserved

1110

This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.

BYPASS

1111

Selects bypass register for data operations

58.4.4.1 IDCODE instruction

IDCODE selects the 32-bit device identification register as the shift path between TDI
and TDO. This instruction allows interrogation of the MCU to determine its version
number and other part identification data. IDCODE is the instruction placed into the
instruction register when the JTAGC block is reset.

58.4.4.2 EZPORT instruction

The EZPORT instruction allows for the EZPORT module to program the on-chip flash
from a simple 4-pin interface. The JTAGC forces the core into a reset state and forces the
EZPORT mode select/chip select low. In this mode, the flash can be programmed
through the JTAG test port pins, which are connected to the EZPORT module.

58.4.4.3 SAMPLE/PRELOAD instruction

The SAMPLE/PRELOAD instruction has two functions:

• The SAMPLE portion of the instruction obtains a sample of the system data and

control signals present at the MCU input pins and just before the boundary scan
register cells at the output pins. This sampling occurs on the rising edge of TCK in
the Capture-DR state when the SAMPLE/PRELOAD instruction is active. The
sampled data is viewed by shifting it through the boundary scan register to the TDO
output during the Shift-DR state. Both the data capture and the shift operation are
transparent to system operation.

• The PRELOAD portion of the instruction initializes the boundary scan register cells

before selecting the EXTEST or CLAMP instructions to perform boundary scan
tests. This is achieved by shifting in initialization data to the boundary scan register
during the Shift-DR state. The initialization data is transferred to the parallel outputs

Functional description

K53 Sub-Family Reference Manual, Rev. 6, Nov 2011

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Freescale Semiconductor, Inc.

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Содержание K53 Series

Страница 1: ...K53 Sub Family Reference Manual Supports MK53DN512ZCLQ10 MK53DN512ZCMD10 MK53DX256ZCLQ10 MK53DX256ZCMD10 Document Number K53P144M100SF2RM Rev 6 Nov 2011...

Страница 2: ...K53 Sub Family Reference Manual Rev 6 Nov 2011 2 Freescale Semiconductor Inc...

Страница 3: ...duction 61 2 3 Module Functional Categories 61 2 3 1 ARM Cortex M4 Core Modules 63 2 3 2 System Modules 63 2 3 3 Memories and Memory Interfaces 64 2 3 4 Clocks 65 2 3 5 Security and Integrity modules...

Страница 4: ...ar Switch Configuration 86 3 3 7 Memory Protection Unit MPU Configuration 89 3 3 8 Peripheral Bridge Configuration 91 3 3 9 DMA request multiplexer configuration 93 3 3 10 DMA Controller Configuration...

Страница 5: ...BAT Register File Configuration 111 3 5 7 EzPort Configuration 112 3 5 8 FlexBus Configuration 113 3 6 Security 116 3 6 1 CRC Configuration 116 3 6 2 MMCAU Configuration 117 3 6 3 RNG Configuration 11...

Страница 6: ...guration 141 3 8 5 CMT Configuration 143 3 8 6 RTC configuration 144 3 9 Communication interfaces 145 3 9 1 Ethernet Configuration 145 3 9 2 Universal Serial Bus USB Subsystem 147 3 9 3 SPI configurat...

Страница 7: ...istribution 5 1 Introduction 183 5 2 Programming model 183 5 3 High Level device clocking diagram 183 5 4 Clock definitions 184 5 4 1 Device clock summary 185 5 5 Internal clocking requirements 187 5...

Страница 8: ...ions 203 6 3 4 Boot sequence 204 Chapter 7 Power Management 7 1 Introduction 207 7 2 Power modes 207 7 3 Entering and exiting power modes 209 7 4 Power mode transitions 210 7 5 Power modes shutdown se...

Страница 9: ...JTAG status and control registers 224 9 5 1 MDM AP Control Register 225 9 5 2 MDM AP Status Register 227 9 6 Debug Resets 228 9 7 AHB AP 229 9 8 ITM 230 9 9 Core Trace Connectivity 230 9 10 Embedded T...

Страница 10: ...45 10 4 2 System Modules 246 10 4 3 Clock Modules 247 10 4 4 Memories and Memory Interfaces 247 10 4 5 Analog 248 10 4 6 Communication Interfaces 250 10 4 7 Human Machine Interfaces HMI 257 Chapter 11...

Страница 11: ...ions 278 12 2 Memory map and register definition 278 12 2 1 System Options Register 1 SIM_SOPT1 280 12 2 2 System Options Register 2 SIM_SOPT2 282 12 2 3 System Options Register 4 SIM_SOPT4 284 12 2 4...

Страница 12: ...IDML 311 12 2 22 Unique Identification Register Low SIM_UIDL 312 12 3 Functional description 312 Chapter 13 Mode Controller 13 1 Introduction 313 13 1 1 Features 313 13 1 2 Modes of Operation 313 13 1...

Страница 13: ...l Descriptions 346 15 3 Memory map register definition 347 15 3 1 LLWU Pin Enable 1 Register LLWU_PE1 347 15 3 2 LLWU Pin Enable 2 Register LLWU_PE2 348 15 3 3 LLWU Pin Enable 3 Register LLWU_PE3 350...

Страница 14: ...68 16 2 7 ETB counter value register MCM_ETBCNT 369 16 3 Functional Description 369 16 3 1 Interrupts 369 Chapter 17 Crossbar Switch AXBS 17 1 Introduction 371 17 1 1 Features 371 17 2 Memory Map Regi...

Страница 15: ...ptor Alternate Access Control n MPU_RGDAACn 399 18 4 Functional Description 401 18 4 1 Access Evaluation Macro 401 18 4 2 Putting It All Together and Error Terminations 402 18 4 3 Power Management 403...

Страница 16: ...3 Always enabled DMA sources 432 20 5 Initialization application information 433 20 5 1 Reset 433 20 5 2 Enabling and configuring sources 433 Chapter 21 Direct Memory Access Controller eDMA 21 1 Intro...

Страница 17: ...op Disabled DMA_TCDn_NBYTES_MLNO 481 21 3 21 TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled DMA_TCDn_NBYTES_MLOFFNO 482 21 3 22 TCD Signed Minor Loop Offset Minor Loop and Offset...

Страница 18: ...4 Performing DMA transfers 505 21 5 5 Monitoring transfer descriptor status 509 21 5 6 Channel Linking 510 21 5 7 Dynamic programming 512 Chapter 22 External Watchdog Monitor EWM 22 1 Introduction 51...

Страница 19: ...7 Debug Modes of Operation 531 23 4 Testing the Watchdog 532 23 4 1 Quick Test 532 23 4 2 Byte Test 532 23 5 Backup Reset Generator 534 23 6 Generated Resets and Interrupts 534 23 7 Memory Map and Re...

Страница 20: ...atures 547 24 1 2 Modes of Operation 550 24 2 External Signal Description 551 24 3 Memory Map Register Definition 551 24 3 1 MCG Control 1 Register MCG_C1 552 24 3 2 MCG Control 2 Register MCG_C2 553...

Страница 21: ...SC 25 1 Introduction 583 25 2 Features and Modes 583 25 3 Block Diagram 584 25 4 OSC Signal Descriptions 584 25 5 External Crystal Resonator Connections 585 25 6 External Clock Connections 586 25 7 Me...

Страница 22: ...1 Introduction 599 27 1 1 Overview 599 27 1 2 Features 600 27 2 Modes of operation 600 27 3 External signal description 600 27 4 Memory map and register descriptions 601 27 4 1 Flash Access Protection...

Страница 23: ...1 Introduction 629 28 1 1 Features 630 28 1 2 Block Diagram 632 28 1 3 Glossary 633 28 2 External Signal Description 635 28 3 Memory Map and Registers 635 28 3 1 Flash Configuration Field Description...

Страница 24: ...ects FB_CS 5 0 705 29 2 3 Byte Enables FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 706 29 2 4 Output Enable FB_OE 706 29 2 5 Read Write FB_R W 706 29 2 6 Transfer Start Address Latch Enable FB_TS FB_...

Страница 25: ...Initialization Application Information 750 29 5 1 Initializing a Chip Select 750 29 5 2 Reconfiguring a Chip Select 750 Chapter 30 EzPort 30 1 Overview 751 30 1 1 Introduction 751 30 1 2 Features 752...

Страница 26: ...tional description 768 31 3 1 CRC initialization re initialization 768 31 3 2 CRC calculations 768 31 3 3 Transpose feature 769 31 3 4 CRC result complement 771 Chapter 32 Memory Mapped Cryptographic...

Страница 27: ...ode 794 33 2 2 Seed Generation Mode 795 33 2 3 Random Number Generation Mode 795 33 3 Memory Map Register Definition 795 33 3 1 RNGB Version ID Register RNG_VER 796 33 3 2 RNGB Command Register RNG_CM...

Страница 28: ...egister 1 ADCx_CFG1 819 34 3 3 Configuration register 2 ADCx_CFG2 821 34 3 4 ADC data result register ADCx_Rn 822 34 3 5 Compare value registers ADCx_CVn 823 34 3 6 Status and control register 2 ADCx_...

Страница 29: ...minus side general calibration value register ADCx_CLM2 836 34 3 24 ADC minus side general calibration value register ADCx_CLM1 837 34 3 25 ADC minus side general calibration value register ADCx_CLM0...

Страница 30: ...r Definitions 870 35 7 1 CMP Control Register 0 CMPx_CR0 871 35 7 2 CMP Control Register 1 CMPx_CR1 872 35 7 3 CMP Filter Period Register CMPx_FPR 873 35 7 4 CMP Status and Control Register CMPx_SCR 8...

Страница 31: ...Data High Register DACx_DATnH 901 36 4 3 DAC Status Register DACx_SR 901 36 4 4 DAC Control Register DACx_C0 902 36 4 5 DAC Control Register 1 DACx_C1 903 36 4 6 DAC Control Register 2 DACx_C2 904 36...

Страница 32: ...g PGA Configuration 918 Chapter 38 Transimpedance Amplifier TRIAMP 38 1 Introduction 921 38 1 1 Features 921 38 1 2 Module operation in low power modes 921 38 1 3 Block Diagram 922 38 1 4 Signal Descr...

Страница 33: ...EFEN 1 932 39 4 Initialization Application Information 933 Chapter 40 Programmable Delay Block PDB 40 1 Introduction 935 40 1 1 Features 935 40 1 2 Implementation 936 40 1 3 Back to back Acknowledgeme...

Страница 34: ...Trigger Outputs 950 40 4 2 PDB Trigger Input Source Selection 952 40 4 3 DAC Interval Trigger Outputs 952 40 4 4 Pulse Out s 953 40 4 5 Updating the Delay Registers 953 40 4 6 Interrupts 955 40 4 7 DM...

Страница 35: ...2 Initial State for Channels Output FTMx_OUTINIT 984 41 3 13 Output Mask FTMx_OUTMASK 985 41 3 14 Function for Linked Channels FTMx_COMBINE 987 41 3 15 Deadtime Insertion Control FTMx_DEADTIME 992 41...

Страница 36: ...uffers 1037 41 4 11 PWM Synchronization 1039 41 4 12 Inverting 1055 41 4 13 Software Output Control 1056 41 4 14 Deadtime Insertion 1058 41 4 15 Output Mask 1061 41 4 16 Fault Control 1062 41 4 17 Pol...

Страница 37: ...ntrol Register PIT_MCR 1096 42 3 2 Timer Load Value Register PIT_LDVALn 1097 42 3 3 Current Timer Value Register PIT_CVALn 1097 42 3 4 Timer Control Register PIT_TCTRLn 1098 42 3 5 Timer Flag Register...

Страница 38: ...4 7 LPTMR interrupt 1113 Chapter 44 Carrier Modulator Transmitter CMT 44 1 Introduction 1115 44 2 Features 1115 44 3 Block Diagram 1116 44 4 Modes of Operation 1117 44 4 1 Wait Mode Operation 1118 44...

Страница 39: ...r 1132 44 7 4 Extended Space Operation 1136 44 8 CMT Interrupts and DMA 1137 Chapter 45 Real Time Clock RTC 45 1 Introduction 1139 45 1 1 Features 1139 45 1 2 Modes of operation 1139 45 1 3 RTC signal...

Страница 40: ...ion 1161 46 3 Memory Map Register Definition 1163 46 3 1 Interrupt Event Register ENET_EIR 1166 46 3 2 Interrupt Mask Register ENET_EIMR 1168 46 3 3 Receive Descriptor Active Register ENET_RDAR 1171 4...

Страница 41: ...most Empty Threshold ENET_RAEM 1189 46 3 25 Receive FIFO Almost Full Threshold ENET_RAFL 1189 46 3 26 Transmit FIFO Section Empty Threshold ENET_TSEM 1190 46 3 27 Transmit FIFO Almost Empty Threshold...

Страница 42: ...acket Detection 1227 46 4 8 IP Accelerator Functions 1228 46 4 9 Resets and Stop Controls 1233 46 4 10 IEEE 1588 Functions 1236 46 4 11 FIFO Thresholds 1239 46 4 12 Loopback Options 1242 46 4 13 Legac...

Страница 43: ...gister USBx_OTGISTAT 1277 47 4 6 OTG Interrupt Control Register USBx_OTGICR 1278 47 4 7 OTG Status Register USBx_OTGSTAT 1279 47 4 8 OTG Control Register USBx_OTGCTL 1280 47 4 9 Interrupt Status Regis...

Страница 44: ...TG Dual Role A Device Operation 1301 47 7 2 OTG Dual Role B Device Operation 1302 Chapter 48 USB Device Charger Detection Module USBDCD 48 1 Preface 1305 48 1 1 References 1305 48 1 2 Acronyms and Abb...

Страница 45: ...B Voltage Regulator 49 1 Introduction 1331 49 1 1 Overview 1331 49 1 2 Features 1332 49 1 3 Modes of Operation 1333 49 2 USB Voltage Regulator Module Signal Descriptions 1333 Chapter 50 SPI DSPI 50 1...

Страница 46: ...Mode SPIx_PUSHR 1359 50 3 8 DSPI PUSH TX FIFO Register In Slave Mode SPIx_PUSHR_SLAVE 1361 50 3 9 DSPI POP RX FIFO Register SPIx_POPR 1361 50 3 10 DSPI Transmit FIFO Registers SPIx_TXFRn 1362 50 3 11...

Страница 47: ...r I2Cx_S 1396 51 3 5 I2C Data I O register I2Cx_D 1398 51 3 6 I2C Control Register 2 I2Cx_C2 1399 51 3 7 I2C Programmable Input Glitch Filter register I2Cx_FLT 1400 51 3 8 I2C Range Address register I...

Страница 48: ...ARTx_BDL 1436 52 3 3 UART Control Register 1 UARTx_C1 1437 52 3 4 UART Control Register 2 UARTx_C2 1439 52 3 5 UART Status Register 1 UARTx_S1 1441 52 3 6 UART Status Register 2 UARTx_S2 1444 52 3 7 U...

Страница 49: ...6T0 1467 52 3 27 UART 7816 Wait Parameter Register UARTx_WP7816T1 1468 52 3 28 UART 7816 Wait N Register UARTx_WN7816 1469 52 3 29 UART 7816 Wait FD Register UARTx_WF7816 1469 52 3 30 UART 7816 Error...

Страница 50: ...gital host controller SDHC 53 1 Introduction 1515 53 2 Overview 1515 53 2 1 Supported types of cards 1515 53 2 2 SDHC block diagram 1516 53 2 3 Features 1517 53 2 4 Modes and operations 1518 53 3 SDHC...

Страница 51: ...DHC_FEVT 1559 53 4 20 ADMA Error Status Register SDHC_ADMAES 1562 53 4 21 ADMA System Address Register SDHC_ADSADDR 1564 53 4 22 Vendor Specific Register SDHC_VENDOR 1564 53 4 23 MMC Boot Register SDH...

Страница 52: ...7 7 Change clock frequency 1621 53 7 8 Multi block read 1621 Chapter 54 Integrated interchip sound I2S 54 1 Introduction 1623 54 1 1 Block diagram 1623 54 1 2 Features 1624 54 1 3 Modes of operation 1...

Страница 53: ...Mask Register I2Sx_TMSK 1663 54 3 18 I2S Receive Time Slot Mask Register I2Sx_RMSK 1663 54 3 19 I2S AC97 Channel Status Register I2Sx_ACCST 1664 54 3 20 I2S AC97 Channel Enable Register I2Sx_ACCEN 16...

Страница 54: ...703 55 3 1 General purpose input 1703 55 3 2 General purpose output 1703 Chapter 56 Touch sense input TSI 56 1 Introduction 1705 56 2 Features 1705 56 3 Overview 1706 56 3 1 Electrode capacitance meas...

Страница 55: ...sitivity 1733 Chapter 57 LCD Controller SLCD 57 1 Introduction 1735 57 1 1 Features 1735 57 1 2 Modes of operation 1736 57 1 3 Block diagram 1737 57 2 LCD Signal Descriptions 1738 57 2 1 LCD_P 63 0 17...

Страница 56: ...LCD waveform register LCD_WF43TO40 1758 57 3 18 LCD waveform register LCD_WF47TO44 1758 57 3 19 LCD waveform register LCD_WF51TO48 1759 57 3 20 LCD waveform register LCD_WF55TO52 1759 57 3 21 LCD wave...

Страница 57: ...ta input 1804 58 2 3 TDO Test data output 1804 58 2 4 TMS Test mode select 1804 58 3 Register description 1805 58 3 1 Instruction register 1805 58 3 2 Bypass register 1805 58 3 3 Device identification...

Страница 58: ...K53 Sub Family Reference Manual Rev 6 Nov 2011 58 Freescale Semiconductor Inc...

Страница 59: ...fy different numbering systems This suffix Identifies a b Binary number For example the binary equivalent of the number 5 is written 101b In some cases binary numbers are shown with the prefix 0b d De...

Страница 60: ...6 4 XAD 7 0 Numbers in brackets and separated by a colon represent either A subset of a register s named field For example REVNO 6 4 refers to bits 6 4 that are part of the COREREV field that occupies...

Страница 61: ...sh in 64LQFP packages extending up to 512 KB in a 144MAPBGA package with a rich suite of analog communication timing and control peripherals High memory density K50 family devices include IEEE1588 Eth...

Страница 62: ...ternally generated clocks System oscillator to provide clock source for the MCU RTC oscillator to provide clock source for the RTC Security Cyclic Redundancy Check module for error detection Hardware...

Страница 63: ...VIC implement a relocatable vector table supporting many external interrupts a single non maskable interrupt NMI and priority levels The NVIC replaces shadow registers with equivalent system and simpl...

Страница 64: ...ong the bus masters when they access the same slave Memory protection unit MPU The MPU provides memory protection and task isolation It concurrently monitors all bus master transactions for the slave...

Страница 65: ...ndustry standard SPI flash memories Provides the ability to read erase and program flash memory and reset command to boot the system after flash programming FlexBus External bus interface with multipl...

Страница 66: ...range of the supply voltage 6 bit digital to analog converters DAC 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed 12 bi...

Страница 67: ...of hardware triggers Software control of PWM outputs Up to 4 fault inputs for global fault control Configurable channel polarity Programmable interrupt on input capture reference compare overflowed co...

Страница 68: ...output that powers on chip USB subsystem capable of sourcing 120 mA to external board components Serial peripheral interface SPI Synchronous serial bus for communication to an external device Inter in...

Страница 69: ...numeric or custom LCD panels Supports 3V or 5V LCD panels 2 4 Orderable part numbers The following table summarizes the part numbers of the devices covered by this document Table 2 11 Orderable part...

Страница 70: ...Orderable part numbers K53 Sub Family Reference Manual Rev 6 Nov 2011 70 Freescale Semiconductor Inc...

Страница 71: ...module to module interactions not necessarily discussed in the individual module chapters and links for more information Core modules 3 2 1 ARM Cortex M4 Core Configuration This section summarizes how...

Страница 72: ...switch Crossbar switch System instruction data bus module SRAM SRAM Debug IEEE 1149 1 JTAG IEEE 1149 7 JTAG cJTAG Serial Wire Debug SWD ARM Real Time Trace Interface Debug Interrupts Nested Vectored I...

Страница 73: ...lock FCLK This results in the following The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock Because the timing reference FCLK is a variable frequency the TE...

Страница 74: ...Power management Power management Private Peripheral Bus PPB ARM Cortex M4 core ARM Cortex M4 core 3 2 2 1 Interrupt priority levels This device supports 16 priority levels for interrupts Therefore in...

Страница 75: ...ARM core Hard Fault 0x0000_0010 4 ARM core MemManage Fault 0x0000_0014 5 ARM core Bus Fault 0x0000_0018 6 ARM core Usage Fault 0x0000_001C 7 0x0000_0020 8 0x0000_0024 9 0x0000_0028 10 0x0000_002C 11...

Страница 76: ...A DMA error interrupt channels 0 15 0x0000_0084 33 17 0 4 MCM Normal interrupt 0x0000_0088 34 18 0 4 Flash memory Command complete 0x0000_008C 35 19 0 4 Flash memory Read collision 0x0000_0090 36 20 0...

Страница 77: ...s 0x0000_0100 64 48 1 12 UART1 Single interrupt vector for UART error sources 0x0000_0104 65 49 1 12 UART2 Single interrupt vector for UART status sources 0x0000_0108 66 50 1 12 UART2 Single interrupt...

Страница 78: ...000_015C 87 71 2 17 PIT Channel 3 0x0000_0160 88 72 2 18 PDB 0x0000_0164 89 73 2 18 USB OTG 0x0000_0168 90 74 2 18 USB Charger Detect 0x0000_016C 91 75 2 18 Ethernet MAC IEEE 1588 Timer Interrupt 0x00...

Страница 79: ...interrupt can only be pended or cleared via the NVIC registers 3 2 2 3 1 Determining the bitfield and register location for configuring a particular interrupt Suppose you need to configure the low pow...

Страница 80: ...5 12 3 2 3 Asynchronous Wake up Interrupt Controller AWIC Configuration This section summarizes how the module has been configured in the chip Full documentation for this module is provided by ARM and...

Страница 81: ...in interrupts Port Control Module Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source CMPx Since no system clocks are available functi...

Страница 82: ...odule has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Register access Peripheral bridge System integration module SIM Figure 3 5...

Страница 83: ...Table 3 10 Reference links to related information Topic Related module Reference Full description Mode Controller Mode Controller System memory map System memory map Power management Power management...

Страница 84: ...ation This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Low Leakage Wake up Unit LLWU Power...

Страница 85: ...ol Table 3 13 Wakeup sources for LLWU inputs Input Wakeup source Input Wakeup source LLWU_P0 PTE1 LLWU_P0 pin LLWU_P12 PTD0 LLWU_P12 pin LLWU_P1 PTE2 LLWU_P1 pin LLWU_P13 PTD2 LLWU_P13 pin LLWU_P2 PTE...

Страница 86: ...s been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Miscellaneous Control Module MCM Transfers ARM Cortex M4 core PPB Figure 3 9 MCM c...

Страница 87: ...n Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Memory protection MPU MPU Crossbar switch master ARM Cortex M4 core ARM Cortex M4 core Crossbar switch...

Страница 88: ...ort share a master port Since these modules never operate at the same time no configuration or arbitration explanations are necessary 3 3 6 2 Crossbar Switch Slave Assignments The slaves connected to...

Страница 89: ...Unit MPU MPU System memory map System memory map Clocking Clock distribution Power management Power management Logical masters Logical master assignments Slave modules Slave module assignments 3 3 7...

Страница 90: ...Handler Control and State Register s BUSFAULTENA bit If this bit is not set MPU violations result in a hard fault interrupt vector 3 Debugger The STICKYERROR flag is set in the Debug Port Control Stat...

Страница 91: ...ermission fields associated with the other masters These protections summarized below guarantee that the debugger always has access to the entire address space and those rights cannot be changed by th...

Страница 92: ...The peripheral bridges are used to access the registers of most of the modules on this device See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot assignment for each module 3 3 8 3 MPRA reg...

Страница 93: ...nding module s PACR 32 127 field resets to 0x4 3 3 9 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the...

Страница 94: ...iption 0 Channel disabled1 1 Reserved Not used 2 UART0 Receive 3 UART0 Transmit 4 UART1 Receive 5 UART1 Transmit 6 UART2 Receive 7 UART2 Transmit 8 UART3 Receive 9 UART3 Transmit 10 UART4 Receive 11 U...

Страница 95: ...hannel 3 40 ADC0 41 ADC1 42 CMP0 43 CMP1 44 CMP2 45 DAC0 46 DAC1 47 CMT 48 PDB 49 Port control module Port A 50 Port control module Port B 51 Port control module Port C 52 Port control module Port D 5...

Страница 96: ...ummarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter DMA Controller Crossbar switch Requests Peripheral brid...

Страница 97: ...ed module Reference Full description External Watchdog Monitor EWM EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Contro...

Страница 98: ...e When the CPU enters Run mode from Power Down the pin returns to its reset state 3 3 12 Watchdog Configuration This section summarizes how the module has been configured in the chip For a comprehensi...

Страница 99: ...DOG low power modes Module mode Chip mode Wait Wait VLPW Standby Stop VLPS Stop Stop VLPS Power Down LLS VLLSx NOTE To enable the WDOG module when the chip is in Stop mode write ones to both the STNDB...

Страница 100: ...iplexing 3 4 2 OSC Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal m...

Страница 101: ...tion of the module itself see the module s dedicated chapter Signal multiplexing 32 kHz RTC oscillator MCG Module signals Figure 3 19 RTC OSC configuration Table 3 34 Reference links to related inform...

Страница 102: ...memory that can execute program code FlexMemory encompasses the following memory types For devices with FlexNVM FlexNVM Non volatile flash memory that can execute program code store data or backup EEP...

Страница 103: ...wap is disabled default configuration 3 5 1 3 Flash Memory Size Considerations Since this document covers devices that contain program flash only and devices that contain program flash and FlexNVM the...

Страница 104: ...field FlexNVM base address Program flash base address Flash memory base address Registers FlexNVM FlexRAM FlexRAM base address Figure 3 22 Flash memory map for devices containing FlexNVM 3 5 1 5 Flash...

Страница 105: ...ition 3 5 2 Flash Memory Controller Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated...

Страница 106: ...signments 3 5 2 2 Program Flash Swap On devices that contain program flash memory only the program flash memory blocks may swap their base addresses While not using swap FMC_PFB0CR controls the lower...

Страница 107: ...M4 core The amount of SRAM for the devices covered in this document is shown in the following table Device SRAM KB MK53DN512ZCLQ10 128 MK53DN512ZCMD10 128 MK53DX256ZCLQ10 64 MK53DX256ZCMD10 64 3 5 3...

Страница 108: ...0x1FFF_FFFF SRAM_U 0x2000_0000 0x2000_7FFF 3 5 3 3 SRAM retention in low power modes The SRAM is retained down to VLLS3 mode In VLLS2 the 4 KB region of SRAM_U from 0x2000_0000 is powered In VLLS1 no...

Страница 109: ...and non core master NOTE Two non core masters cannot access SRAM simultaneously The required arbitration and serialization is provided by the crossbar switch The SRAM_ L U arbitration is controlled by...

Страница 110: ...formation Topic Related module Reference System memory map System memory map Power management Power management Power management controller PMC PMC Transfers SRAM SRAM ARM Cortex M4 core ARM Cortex M4...

Страница 111: ...stribution Power management Power management 3 5 5 1 System Register file This device includes a 32 byte register file that is powered in all power modes Also it retains contents during low voltage de...

Страница 112: ...ll power modes and is powered by VBAT It is only reset during VBAT power on reset 3 5 7 EzPort Configuration This section summarizes how the module has been configured in the chip For a comprehensive...

Страница 113: ...bit is cleared then the state of the chip select signal EZP_CS is ignored and the MCU always boots in normal mode This option is useful for systems that use the EZP_CS NMI signal configured for its N...

Страница 114: ...lexBus module s external FB_CLKOUT Its clock frequency is derived from a divider of the MCGOUTCLK See Clock Distribution for more details 3 5 8 2 FlexBus signal multiplexing The multiplexing of the Fl...

Страница 115: ...modules External Pins FB_ALE Reserved FB_TSIZ0 Reserved FB_TSIZ1 Reserved Reserved Reserved FB_CS1 FB_TS FB_CS4 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 FB_CS5 FB_TBST FB_CS2 FB_TA FB_CS3 Figure 3...

Страница 116: ...lexBus access 3 5 8 4 FlexBus Security When security is enabled on the device FlexBus accesses may be restricted by configuring the FBSEL field in the SIM s SOPT2 register See System Integration Modul...

Страница 117: ...chip For a comprehensive description of the module itself see the module s dedicated chapter MMCAU Transfers ARM Cortex M4 Core PPB Figure 3 34 MMCAU configuration Table 3 44 Reference links to relate...

Страница 118: ...ence links to related information Topic Related module Reference Full description RNG RNG System memory map System memory map Clocking Clock distribution Power management Power management Analog 3 7 1...

Страница 119: ...te PGAs 3 7 1 1 1 Number of ADC channels The number of ADC channels present on the device is determined by the pinout of the specific device package For details regarding the number of ADC channel ava...

Страница 120: ...d 001115 AD7a Reserved Reserved 001005 AD4b Reserved ADC0_SE4b 001015 AD5b Reserved ADC0_SE5b 001105 AD6b Reserved ADC0_SE6b 001115 AD7b Reserved ADC0_SE7b 01000 AD8 Reserved ADC0_SE86 01001 AD9 Reser...

Страница 121: ...l ensure that you enable the bandgap buffer by setting the PMC_REGSC BGBE bit Refer to the device data sheet for the bandgap voltage VBG specification 3 7 1 4 ADC1 Connections Channel Assignment NOTE...

Страница 122: ...E 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled 1 Interleaved with ADC0_DP3 and ADC0_DM3 2 Interleaved with ADC0_DP3 3 Interleaved with ADC0_DP0 and ADC0_DM0 4 Interleaved with...

Страница 123: ...nnels The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration ADC0 AD8 AD9 ADC1 AD8 AD9 ADC0_SE8 ADC1_SE8 ADC0_SE9 ADC1_SE9 Figure 3 38 ADC hardware interleaved...

Страница 124: ...connected to the PDB The PDB trigger can receive the RTC alarm seconds trigger input forcing ADC conversions in run mode where PDB is enabled On the other hand the ADC can conduct conversions in low p...

Страница 125: ...it is part of the ADC and is selected as a separate channel Each PGA connects to the differential ADC channels The PGA outputs differential pairs that are connected to ADC differential input When the...

Страница 126: ...C1_DM0 ADC0_DM3 ADC1_DP1 ADC1_DM1 ADC0_DP1 ADC0_DM1 Figure 3 39 PGA Integration 3 7 2 CMP Configuration This section summarizes how the module has been configured in the chip For a comprehensive descr...

Страница 127: ...tions to the CMP CMP Inputs CMP0 CMP1 CMP2 IN0 CMP0_IN0 CMP1_IN0 CMP2_IN0 IN1 CMP0_IN1 CMP1_IN1 CMP2_IN1 IN2 CMP0_IN2 Op amp 0 output CMP1_IN2 Op amp 1 output CMP2_IN2 IN3 CMP0_IN3 12b DAC0 reference...

Страница 128: ...s to related information Topic Related module Reference Full description 12 bit DAC 12 bit DAC System memory map System memory map Clocking Clock distribution Power management Power management Signal...

Страница 129: ...n the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Register access Peripheral bridge Op amp Module signals DAC Input signals CMP Fig...

Страница 130: ...n 0 OP0_DP0 input signal 1 Op amp 0 output 2 Op amp 1 output 3 CMP0 6 bit DAC output 4 12 bit DAC0 output 5 12 bit DAC1 Output 6 VDD 7 Ground 3 7 4 3 Op amp 1 input mux connections The op amp 1 module...

Страница 131: ...vailable as follows Op amp number Op amp output signal connection 0 CMP1 input 0 ADC0 channel 0 OP0_OUT output signal 1 CMP2 input 1 ADC0 channel 1 OP1_OUT output signal 3 7 5 TRIAMP Configuration Thi...

Страница 132: ...ng the TRIAMP signals used on this device are as follows The TRIAMP inputs TRIx_DM and TRIx_DP are dedicated low leakage input pads The TRIAMP0 output is driven to external pin TRI0_OUT and is shared...

Страница 133: ...urate 1 2 V voltage output The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals such as the ADC DAC Op amp TRIAMP or CMP NOTE For either a...

Страница 134: ...ultiplexing Port control Signal multiplexing 3 8 1 1 PDB Instantiation 3 8 1 1 1 PDB Output Triggers Table 3 54 PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre triggers per...

Страница 135: ...FTM0 DAC triggers DAC0 and DAC1 trigger Pulse out Pulse out connected to each CMP module s sample window input to control sample operation 3 8 1 3 Back to back acknowledgement connections In this MCU...

Страница 136: ...ger input PDB interval trigger 1 connects to DAC1 hardware trigger input 3 8 1 5 DAC External Trigger Input Connections In this MCU two DAC external trigger inputs are implemented DAC external trigger...

Страница 137: ...apter Signal multiplexing Module signals Register access FlexTimer Peripheral bus controller 0 Other peripherals Transfers Figure 3 47 FlexTimer configuration Table 3 57 Reference links to related inf...

Страница 138: ...OPT4 register in the SIM module 3 8 2 3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK 3 8 2 4 FTM Interrupts The FlexTimer has multiple sources of interrupt However these so...

Страница 139: ...e trigger 2 FTM2_FLT0 pin 3 8 2 7 Input capture options for FTM module instances The following channel 0 input capture source options are selected via the SOPT4 register in the SIM module The external...

Страница 140: ...In the FTM chapter references to the chip being in BDM are the same as the chip being in debug halt mode 3 8 3 PIT Configuration This section summarizes how the module has been configured in the chip...

Страница 141: ...umber PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel 3 3 8 3 2 PIT ADC Triggers PIT triggers are selected as ADCx trigger sou...

Страница 142: ...of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR PCS bitfield The following table shows the chip specific clock assignments for this bitfield NOTE The chosen cl...

Страница 143: ...scription of the module itself see the module s dedicated chapter Signal multiplexing Module signals Register access CMT Peripheral bus controller 0 Figure 3 51 CMT configuration Table 3 62 Reference...

Страница 144: ...itself see the module s dedicated chapter Signal multiplexing Register access Peripheral bridge Module signals Real time clock Figure 3 52 RTC configuration Table 3 63 Reference links to related info...

Страница 145: ...uration Table 3 64 Reference links to related information Topic Related module Reference Full description Ethernet Ethernet System memory map System memory map Clocking Clock Distribution Transfers Cr...

Страница 146: ...ompare value The counter is able to operate asynchronously to the ethernet bus by using one of four clock sources See Ethernet Clocking for more details 3 9 1 4 Ethernet Operation in Low Power Modes T...

Страница 147: ...for a summary Interrupt request Interrupt source IEEE 1588 timer interrupt Time stamp available 1588 timer interrupt Transmit interrupt Transmit frame interrupt Transmit buffer interrupt Receive inte...

Страница 148: ...3 ms the INT_STAT SLEEP bit is set This bit can cause an interrupt and software decides the appropriate action Waking from a low power mode except in LLS VLLS mode where USB is not powered occurs thr...

Страница 149: ...n battery In this case VOUT33 is connected to VDD The USB regulator must be enabled by default to power the MCU When connected to a USB host the input source of this regulator is switched to the USB b...

Страница 150: ...an also be powered by the USB bus directly In this case VOUT33 is connected to VDD The USB regulator must be enabled by default to power the MCU then to power USB transceiver or external sensor USB Re...

Страница 151: ...n Table 3 65 Reference links to related information Topic Related module Reference Full description USB controller USB controller System memory map System memory map Clocking Clock Distribution Transf...

Страница 152: ...ured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multiplexing Module signals USB Voltage Regulator USB OTG Figure 3 60 USB Voltage Regula...

Страница 153: ...eference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Mu...

Страница 154: ...the slave transfer attributes 3 9 3 4 TX FIFO size Table 3 69 SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 4 SPI1 4 SPI2 4 3 9 3 5 RX FIFO Size SPI supports up to 16 bit frame size durin...

Страница 155: ...use a GPIO to create a wakeup upon reception of SPI data in slave mode 1 Point the GPIO interrupt vector to the desired interrupt handler 2 Enable the GPIO input to generate an interrupt on either the...

Страница 156: ...ck 3 9 4 I2C Configuration This section summarizes how the module has been configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Signal multipl...

Страница 157: ...map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing 3 9 5 1 UART configuration information This device contains six UART modules Thi...

Страница 158: ...to generate a single interrupt request See below for the mapping of the individual interrupt sources to the interrupt request The status interrupt combines the following interrupt sources Source UART...

Страница 159: ...n configured in the chip For a comprehensive description of the module itself see the module s dedicated chapter Crossbar switch Register access Peripheral bridge Module signals SDHC Transfers Signal...

Страница 160: ...SD clock to be pulled up during data transfers The SDHC also provides a feature of detecting card insertion removal by detecting voltage level changes on DAT 3 of the SD bus To support this DAT 3 must...

Страница 161: ...ignal Multiplexing NOTE The I2S master clock can be output on the I2S0_MCLK pin or input on the I2S0_CLKIN pin Using the I2S0_RX_BCLK pin to output the I2S master clock in synchronous mode is not supp...

Страница 162: ...tails 3 9 7 4 I2S operation in low power modes The I2S module requires interaction with the rest of the system to move data in or out of the FIFOs Since the rest of the system is not active in stop VL...

Страница 163: ...ignal Multiplexing 3 10 1 1 GPIO access protection The GPIO module does not have access protection because it is not connected to a peripheral bridge slot and is not protected by the MPU 3 10 1 2 Numb...

Страница 164: ...one selectable pin is active 3 10 2 2 TSI module functionality in MCU operation modes Table 3 79 TSI module functionality in MCU operation modes MCU operation mode TSI clock sources TSI operation mode...

Страница 165: ...This table shows the TSI clocks and the corresponding chip clocks Table 3 80 TSI clock connections Module clock Chip clock BUSCLK Bus clock MCGIRCLK MCGIRCLK OSCERCLK OSCERCLK LPOCLK 1 kHz LPO clock V...

Страница 166: ...nagement Power management Signal multiplexing Port control Signal multiplexing 3 10 3 1 Instantiation information The following table lists the Segment LCD SLCD support information Table 3 82 SLCD sup...

Страница 167: ...shows the LCD clock and the corresponding chip clock source Table 3 84 LCD clock source Module clock Chip clock Default clock external crystal or reference clock Default clock is either the system OSC...

Страница 168: ...Human machine interfaces HMI K53 Sub Family Reference Manual Rev 6 Nov 2011 168 Freescale Semiconductor Inc...

Страница 169: ...FF For MK53DN512ZCLQ10 Reserved For MK53DN512ZCMD10 Reserved For MK53DX256ZCLQ10 FlexNVM For MK53DX256ZCMD10 FlexNVM All masters 0x1400_0000 0x17FF_FFFF For devices with FlexNVM FlexRAM For devices wi...

Страница 170: ...cess rights to AIPS Lite peripheral bridges and general purpose input output GPIO module address space is limited to the core DMA and EzPort 2 ARM Cortex M4 core access privileges also includes access...

Страница 171: ...band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit band region 4 3 Flash Memory Map The various flash memories and the flash registe...

Страница 172: ...taining FlexNVM 4 3 1 Alternate Non Volatile IRC User Trim Description The following non volatile locations 4 bytes are reserved for custom IRC user trim supported by some development tools An alterna...

Страница 173: ...sible at locations 0x4000_0000 0x4007_FFFF AIPS Lite1 and the general purpose input output module share the connection to crossbar switch slave port 3 The AIPS Lite1 is accessible at locations 0x4008_...

Страница 174: ...l descriptors 0x4000_A000 10 0x4000_B000 11 0x4000_C000 12 FlexBus 0x4000_D000 13 MPU 0x4000_E000 14 0x4000_F000 15 0x4001_0000 16 0x4001_1000 17 0x4001_2000 18 0x4001_3000 19 0x4001_4000 20 0x4001_50...

Страница 175: ...003_2000 50 CRC 0x4003_3000 51 0x4003_4000 52 0x4003_5000 53 USB DCD 0x4003_6000 54 Programmable delay block PDB 0x4003_7000 55 Periodic interrupt timers PIT 0x4003_8000 56 FlexTimer FTM 0 0x4003_9000...

Страница 176: ...D000 77 Port E multiplexing control 0x4004_E000 78 0x4004_F000 79 0x4005_0000 80 0x4005_1000 81 0x4005_2000 82 Software watchdog 0x4005_3000 83 0x4005_4000 84 0x4005_5000 85 0x4005_6000 86 0x4005_7000...

Страница 177: ...tal to analog converter DAC 0x4007_4000 116 Voltage reference VREF 0x4007_5000 117 0x4007_6000 118 0x4007_7000 119 0x4007_8000 120 0x4007_9000 121 0x4007_A000 122 0x4007_B000 123 0x4007_C000 124 Low l...

Страница 178: ...14 0x4008_F000 15 0x4009_0000 16 0x4009_1000 17 0x4009_2000 18 0x4009_3000 19 0x4009_4000 20 0x4009_5000 21 0x4009_6000 22 0x4009_7000 23 0x4009_8000 24 0x4009_9000 25 0x4009_A000 26 0x4009_B000 27 0...

Страница 179: ...1000 49 SDHC 0x400B_2000 50 0x400B_3000 51 0x400B_4000 52 0x400B_5000 53 0x400B_6000 54 0x400B_7000 55 0x400B_8000 56 FlexTimer FTM 2 0x400B_9000 57 0x400B_A000 58 0x400B_B000 59 Analog to digital con...

Страница 180: ...8 0x400C_F000 79 0x400D_0000 80 0x400D_1000 81 0x400D_2000 82 0x400D_3000 83 0x400D_4000 84 0x400D_5000 85 0x400D_6000 86 0x400D_7000 87 0x400D_8000 88 0x400D_9000 89 0x400D_A000 90 0x400D_B000 91 0x4...

Страница 181: ...116 0x400F_5000 0x400F_5800 117 Subslot A Op amp 0 Subslot B Op amp 1 0x400F_6000 118 0x400F_7000 119 0x400F_8000 0x400F_8800 120 Subslot a TRIAMP 0 Subslot b TRIAMP 1 0x400F_9000 121 0x400F_A000 122...

Страница 182: ...xE000_E000 0xE000_EFFF System Control Space SCS for NVIC 0xE000_F000 0xE003_FFFF Reserved 0xE004_0000 0xE004_0FFF Trace Port Interface Unit TPIU 0xE004_1000 0xE004_1FFF Embedded Trace Macrocell ETM 0x...

Страница 183: ...wer dissipation Various modules such as the USB OTG Controller have module specific clocks that can be generated from the MCGPLLCLK or MCGFLLCLK clock In addition there are various other module specif...

Страница 184: ...e note MCGFLLCLK MCGPLLCLK Note See subsequent sections for details on where these clocks are used PMC logic PMC LPO OSCCLK CG CG CG CG CG CG Clock gate 2 OUTDIV3 FlexBus clock CG Figure 5 1 Clocking...

Страница 185: ...ck Input clock to the MCG sourced by the system oscillator OSCCLK or RTC oscillator OSCCLK System oscillator output of the internal oscillator or sourced directly from EXTAL OSCERCLK System oscillator...

Страница 186: ...or Stop mode and OSC_CR EREFSTEN cleared External reference 32kHz ERCLK32K 30 40 kHz 30 40 kHz System OSC or RTC OSC depending on SIM_SOPT1 OSC32K SEL System OSC s OSC_CR ERCLKEN cleared or RTC s RTC...

Страница 187: ...clocks for this device 1 The core and system clock frequencies must be 100 MHz or slower 2 The bus clock frequency must be programmed to 50 MHz or less and an integer divide of the core clock 3 The f...

Страница 188: ...divide by 2 Fast clock boot This gives the user flexibility for a lower frequency low power boot option The flash erased state defaults to fast clocking mode since where the low power boot FTFL_FOPT...

Страница 189: ...cks associated with each module Table 5 2 Module clocks Module Bus interface clock Internal clocks I O interface clocks Core modules ARM Cortex M4 core System clock Core clock NVIC System clock DAP Sy...

Страница 190: ...Bus clock OSCERCLK CMP Bus clock DAC Bus clock VREF Bus clock Op Amp Bus clock TRIAMP Bus clock Timers PDB Bus clock FlexTimers Bus clock MCGFFCLK FTM_CLKINx PIT Bus clock LPTMR Bus clock LPO OSCERCL...

Страница 191: ...t Controller PMC generates a 1 kHz clock that is enabled in all modes of operation including all low power modes This 1 kHz source is commonly referred to as LPO clock or 1 kHz LPO clock 5 7 2 WDOG cl...

Страница 192: ...an be clocked as shown in the following figure NOTE In stop mode the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source PORTx_DFCR CS PORTx digital in...

Страница 193: ...lied from pins and must be 25 MHz The IEEE 1588 timestamp clock can run up to 100 MHz if generated from internal clock sources Its period must be an integer number of nanoseconds eg 10ns 100 MHz 15ns...

Страница 194: ...CGFLLCLK SIM_CLKDIV2 USBFRAC USBDIV SIM_SOPT2 USBSRC Figure 5 7 USB 48 MHz clock source NOTE The MCGFLLCLK does not meet the USB jitter specifications for certification 5 7 8 UART clocking UART0 and U...

Страница 195: ...is 50 MHz The master clock source can be derived from several sources as shown in the following figure SIM_SOPT2 I2SSRC Core system clock MCGPLLCLK or MCGFLLCLK OSCERCLK S master clock I 2 I2S_CLKIN...

Страница 196: ...SI can be clocked as shown in the following figure NOTE In the TSI chapter these two clocks are referred to as LPOCLK and VLPOSCCLK TSI_GENCS LPCLKS TSI clock in low power mode LPO ERCLK32K Figure 5 1...

Страница 197: ...ach of the system reset sources with the exception of the EzPort and MDM AP reset has an associated bit in the system reset status registers SRSH and SRSL See the Mode controller for more details The...

Страница 198: ...cessor exits reset it performs the following Reads the start SP SP_main from vector table offset 0 Reads the start PC from vector table offset 4 LR is set to 0xFFFF_FFFF The on chip peripheral modules...

Страница 199: ...eup from VLLS The reset value for each filter defaults to off non detect The LPO filter is simple with a fixed filter value count of 3 There is also a synchronizer on the input signal that results in...

Страница 200: ...s LLS mode exits via RESET pin and any VLLS mode exits via a wakeup or reset event the SRSL WAKEUP bit in mode controller module is set indicating the low leakage mode was active prior to the last sys...

Страница 201: ...ate protection hardware The LOCKUP condition causes a system reset and also causes SRSH LOCKUP bit to set 6 2 2 8 EzPort reset The EzPort supports a system reset request via EzPort signalling The EzPo...

Страница 202: ...hine after exiting LLS or VLLSx without resetting the state of the debug modules The nTRST pin does not cause a system reset 6 2 3 3 Resetting the Debug subsystem Use the CDBGRSTREQ bit within the SWJ...

Страница 203: ...device can be in run or various low power modes mentioned in Power mode transitions Table 6 2 Mode select decoding EzPort chip select EZP_CS Description 0 Serial flash programming mode EzPort 1 Singl...

Страница 204: ...re 0xF divide by 16 1 Normal boot OUTDIVx values in SIM_CLKDIV1 register are auto configured at reset exit for higher frequency values that produce faster operating frequencies at reset exit Core and...

Страница 205: ...e of system reset clocking is switched to a slow clock if FTFL_FOPT LPBOOT is configured for Low Power Boot 7 When the system exits reset the processor sets up the stack program counter PC and link re...

Страница 206: ...Boot K53 Sub Family Reference Manual Rev 6 Nov 2011 206 Freescale Semiconductor Inc...

Страница 207: ...run mode there is a corresponding wait and stop mode Wait modes are similar to ARM sleep modes Stop modes VLPS STOP are similar to ARM sleep deep mode The very low power run VLPR operating mode can dr...

Страница 208: ...wer mode that supplies only enough power to run the chip at a reduced frequency All SRAM is operating content retained and I O states held Sleep Deep Interrupt LLS Low Leakage Stop State retention pow...

Страница 209: ...eset an enabled pin or enabled module See the table LLWU inputs in the LLWU configuration section for a list of the sources The wake up flow from VLLSx is through reset The wakeup bit in the SRS regis...

Страница 210: ...frequency but offer a lower power operating mode than normal modes The LLS and VLLSx modes are the lowest power stop modes based on amount of logic or memory that is required to be retained by the app...

Страница 211: ...riven from the on chip regulator as defined for the targeted low power mode In wait modes most of the system clocks are not affected by the low power mode entry The Core Clock to the ARM Cortex M4 cor...

Страница 212: ...c static OFF Clocks 1kHz LPO ON ON ON ON ON ON System oscillator OSC OSCERCLK optional OSCERCLK max of 4MHz crystal OSCERCLK max of 4MHz crystal OSCERCLK max of 4MHz crystal limited to low range low p...

Страница 213: ...static 1 Mbps 1 Mbps static static OFF I2C static address match wakeup 100 kbps 100 kbps static address match wakeup static OFF I2S FF with external clock6 FF FF FF with external clock6 static OFF SDH...

Страница 214: ...ere are no access restrictions for FlexRAM configured as traditional RAM 5 These components remain powered in BAT power mode 6 Use an externally generated bit clock or an externally generated audio ma...

Страница 215: ...e security byte of the flash configuration field NOTE The security features apply only to external accesses debug and EzPort CPU accesses to the flash are not affected by the status of FSEC In the uns...

Страница 216: ...ed to the mass erase Erase All Blocks and verify all 1s Read 1s All Blocks commands Read accesses to internal memories via the EzPort are blocked when security is enabled The mass erase can be used to...

Страница 217: ...When mass erase is disabled mass erase via the debugger is blocked Chapter 8 Security K53 Sub Family Reference Manual Rev 6 Nov 2011 Freescale Semiconductor Inc 217...

Страница 218: ...Security Interactions with other Modules K53 Sub Family Reference Manual Rev 6 Nov 2011 218 Freescale Semiconductor Inc...

Страница 219: ...f the pinout and other available resources Four debug interfaces are supported IEEE 1149 1 JTAG IEEE 1149 7 JTAG cJTAG Serial Wire Debug SWD ARM Real Time Trace Interface The basic Cortex M4 debug arc...

Страница 220: ...G to debug module and SOC system memory maps JTAG AP Bridge to DFT BIST resources ROM Table Identifies which debug IP is available Core Debug Singlestep Register Access Run Core Status CoreSight Trace...

Страница 221: ...he comparators to return a Breakpoint Instruction BKPT to the processor core on a match so providing hardware breakpoint capability TPIU Trace Port Inteface Unit Synchronous Mode 5 pin TRACE_D 3 0 TRA...

Страница 222: ...t The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences Once the mode has been changed unused debug pins can be reassigned to...

Страница 223: ...re Data Pull up JTAG_TCLK SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull down JTAG_TDI I JTAG Test Data Input Pull up JTAG_TDO TRACE_SW O O JTAG Test Data Output O Trace output over...

Страница 224: ...perations Factory debug reserved 0101 0110 0111 Intended for factory debug only ARM JTAG DP Reserved 1000 1010 1011 1110 These instructions will go the ARM JTAG DP controller Please look at ARM JTAG D...

Страница 225: ...Status 0x00 Control 0x01 IDR 0x3F AHB AP SELECT 31 24 0x00 selects the AHB AP See ARM documentation for further details MDM AP SELECT 31 24 0x01 selects the MDM AP SELECT 7 4 0x0 selects the bank with...

Страница 226: ...from reset and CPU operation begins 5 VLLSx Debug Request VLLDBGREQ N Set to configure the system to be held in reset after the next recovery from a VLLSx mode This bit drives directly to the Mode Co...

Страница 227: ...er Flash control logic has started the mass erase operation When mass erase is disabled via MEEN and SEC settings an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged...

Страница 228: ...it is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS VLLSx Status Acknowledge bit in MDM AP Control register 10 VLLSx Modes Exit Th...

Страница 229: ...aborts drive an AHB AP supported sideband signal called HABORT This signal is driven into the Bus Matrix which resets the Bus Matrix state so that AHB AP can access the Private Peripheral Bus for last...

Страница 230: ...e of the Serial Wire Viewer SWV output clocks the counter 4 Global system timestamping Timestamps can optionally be generated using a system wide 48 bit count value The same count value can be used to...

Страница 231: ...apture and flushing APB interface Read write and data pointers provide access to ETB registers In addition the APB interface supports wait states through the use of a PREADYDBG signal output by the ET...

Страница 232: ...s Reload request transfers reload value to counter ATB valid and ready signals used to form counter decrement The counter disarms itself when the count reaches 0 9 12 TPIU The TPIU acts as a bridge be...

Страница 233: ...run to support core register access and trace In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar W...

Страница 234: ...FF FF OFF static OFF ETM FF FF FF OFF static OFF ETB FF FF FF OFF static OFF TPIU FF FF FF OFF static OFF DWT FF FF FF OFF static OFF 9 15 Debug Security When security is enabled FSEC SEC 10 the debu...

Страница 235: ...2 Signal Multiplexing Integration This section summarizes how the module is integrated into the device For a comprehensive description of the module itself see the module s dedicated chapter Register...

Страница 236: ...5 PORTx bits in the SIM module These bits are cleared after any reset which disables the clock to the corresponding module to conserve power Prior to initializing the corresponding module set SCGC5 PO...

Страница 237: ...C1_SE7 a ADC1_SE7 a PTE3 SPI1_SIN UART1_RT S_b SDHC0_CM D FB_AD24 5 E5 VDD VDD VDD 6 F6 VSS VSS VSS 7 E3 PTE4 LLWU_P2 DISABLED PTE4 LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3 FB_CS3_b FB_BE7_0_ BLS31_24_ b F...

Страница 238: ...C0_DM0 ADC1_DM3 PGA0_DM ADC0_DM0 ADC1_DM3 29 M1 PGA1_DP ADC1_DP0 ADC0_DP3 PGA1_DP ADC1_DP0 ADC0_DP3 PGA1_DP ADC1_DP0 ADC0_DP3 30 M2 PGA1_DM ADC1_DM0 ADC0_DM3 PGA1_DM ADC1_DM0 ADC0_DM3 PGA1_DM ADC1_DM0...

Страница 239: ...M6 EXTAL32 EXTAL32 EXTAL32 48 L6 VBAT VBAT VBAT 49 H4 PTE28 DISABLED PTE28 FB_AD20 50 J5 PTA0 JTAG_TCL K SWD_CLK EZP_CLK TSI0_CH1 PTA0 UART0_CT S_b FTM0_CH5 JTAG_TCL K SWD_CLK EZP_CLK 51 J6 PTA1 JTAG...

Страница 240: ...PTA15 SPI0_SCK UART0_RX RMII0_TXE N MII0_TXEN FB_AD30 I2S0_RXD 68 K10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CT S_b RMII0_TXD 0 MII0_TXD0 FB_AD29 I2S0_RX_F S 69 K11 PTA17 ADC1_SE1 7 ADC1_SE1 7 PTA17 SP...

Страница 241: ...LCD_P9 91 E12 PTB10 LCD_P10 ADC1_SE1 4 LCD_P10 ADC1_SE1 4 PTB10 SPI1_PCS0 UART3_RX FTM0_FLT1 LCD_P10 92 E11 PTB11 LCD_P11 ADC1_SE1 5 LCD_P11 ADC1_SE1 5 PTB11 SPI1_SCK UART3_TX FTM0_FLT2 LCD_P11 93 H7...

Страница 242: ...LCD_P25 PTC5 LLWU_P9 SPI0_SCK LPT0_ALT2 CMP0_OUT LCD_P25 115 C8 PTC6 LLWU_P10 LCD_P26 CMP0_IN0 LCD_P26 CMP0_IN0 PTC6 LLWU_P10 SPI0_SOUT PDB0_EXT RG LCD_P26 116 B8 PTC7 LCD_P27 CMP0_IN1 LCD_P27 CMP0_I...

Страница 243: ...D_P45 ADC0_SE6 b PTD5 SPI0_PCS2 UART0_CT S_b FTM0_CH5 EWM_OUT _b LCD_P45 135 A2 PTD6 LLWU_P15 LCD_P46 ADC0_SE7 b LCD_P46 ADC0_SE7 b PTD6 LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0 LCD_P46 136 M10...

Страница 244: ...TB9 PTB8 PTB7 PTA29 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB21 PTA24 RESET_b PTA19 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13 PTA12 PTA11 PTA10 PTA9 PTA8 PTA7 PTA6 VSS VDD PTA5 PTA4 PTA3 PTA2 PTA1 PTA0...

Страница 245: ...PGA1_DM ADC1_DM0 ADC0_DM3 VREF_OUT CMP1_IN5 CMP0_IN5 ADC1_SE18 TRI0_DP TRI1_DP EXTAL32 XTAL32 PTA5 PTA10 VSS PTA16 PTA14 PTB3 PTA29 PTA26 PTA17 PTA15 PTA19 RESET_b PTA24 PTA25 PTA28 PTB2 PTB6 PTB7 PTB...

Страница 246: ...RACE_CLKOUT TRACECLK Trace clock output from the ARM CoreSight debug block O TRACE_D 3 2 TRACEDATA Trace output data from the ARM CoreSight debug block used for 5 pin interface O TRACE_D 1 0 TRACEDATA...

Страница 247: ...p signal name Module signal name Description I O EXTAL0 EXTAL External clock Oscillator input I XTAL0 XTAL Oscillator output O Table 10 8 RTC OSC Signal Descriptions Chip signal name Module signal nam...

Страница 248: ...5_8_BLS23 _16 FB_BE7_0_BLS31_ 24 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 Byte enables O FB_OE FB_OE Output enable O FB_R W FB_R W Read write 1 Read 0 Write O FB_TS FB_ALE FB_TS Transfer start O F...

Страница 249: ...ect low I VDDA VDDA Analog power supply I VSSA VSSA Analog ground I Table 10 13 CMP 0 Signal Descriptions Chip signal name Module signal name Description I O CMP0_IN 5 0 IN 5 0 Analog voltage inputs I...

Страница 250: ...e Description I O OP1_DP0 INPx Amplifier positive input terminal I OP1_DM 2 0 INPx Amplifier negative input terminal I OP1_OUT VOUTx Amplifier output terminal O Table 10 20 TRIAMP 1 Signal Description...

Страница 251: ...RXER I MII0_RXDV MII_RXDV Asserting this input indicates the PHY has valid nibbles present on the MII RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble...

Страница 252: ...ntroller Data is synchronous to MDC This signal is an input after reset I O RMII0_CRS_DV RMII_CRS_DV Asserting this input indicates the PHY has valid nibbles present on the MII RXDV must remain assert...

Страница 253: ...al Descriptions Chip signal name Module signal name Description I O VOUT33 reg33_out Regulator output voltage O VREGIN reg33_in Unregulated power supply I Table 10 24 SPI 0 Signal Descriptions Chip si...

Страница 254: ...al name Module signal name Description I O UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I Table 10 28 UART 1 Signal Descriptions...

Страница 255: ...ta I Table 10 33 SDHC Signal Descriptions Chip signal name Module signal name Description I O SDHC0_CLKIN SDHC clock input I SDHC0_DCLK SDHC_DCLK Generated clock used to drive the MMC SD SDIO or CE AT...

Страница 256: ...used as an input or output The frame sync is used by the receiver to synchronize the transfer of data The frame sync signal can be one bit or one word in length and can occur one bit before the transf...

Страница 257: ...register The STXD port is an output port when data is being transmitted and is disabled between data word transmissions and on the trailing edge of the bit clock after the last bit of a word is transm...

Страница 258: ...LCD_P 63 0 can operate as GPIO pins O VLL 3 1 VLL1 VLL2 VLL3 LCD bias voltages LCD bias voltages I O VCAP 2 1 Vcap1 Vcap2 LCD charge pump capacitance Charge pump capacitor pins O 1 The available LCD...

Страница 259: ...instance of the PORT module for each port Not all pins within each port are implemented on a specific device 11 1 2 Features Pin interrupt Interrupt flag and enable registers for each pin Supports edg...

Страница 260: ...nfiguration registers are functional in all digital pin muxing modes 11 1 3 Modes of operation 11 1 3 1 Run mode In run mode the PORT operates normally 11 1 3 2 Wait mode In wait mode the PORT continu...

Страница 261: ...and can assert asynchronously to the system clock 11 4 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error...

Страница 262: ...00_0000h 11 4 1 268 4004_9048 Pin Control Register n PORTA_PCR18 32 R W 0000_0000h 11 4 1 268 4004_904C Pin Control Register n PORTA_PCR19 32 R W 0000_0000h 11 4 1 268 4004_9050 Pin Control Register n...

Страница 263: ...00h 11 4 1 268 4004_A02C Pin Control Register n PORTB_PCR11 32 R W 0000_0000h 11 4 1 268 4004_A030 Pin Control Register n PORTB_PCR12 32 R W 0000_0000h 11 4 1 268 4004_A034 Pin Control Register n PORT...

Страница 264: ...ter n PORTC_PCR3 32 R W 0000_0000h 11 4 1 268 4004_B010 Pin Control Register n PORTC_PCR4 32 R W 0000_0000h 11 4 1 268 4004_B014 Pin Control Register n PORTC_PCR5 32 R W 0000_0000h 11 4 1 268 4004_B01...

Страница 265: ...0_0000h 11 4 3 271 4004_B0A0 Interrupt Status Flag Register PORTC_ISFR 32 w1c 0000_0000h 11 4 4 271 4004_B0C0 Digital Filter Enable Register PORTC_DFER 32 R W 0000_0000h 11 4 5 272 4004_B0C4 Digital F...

Страница 266: ...n PORTD_PCR26 32 R W 0000_0000h 11 4 1 268 4004_C06C Pin Control Register n PORTD_PCR27 32 R W 0000_0000h 11 4 1 268 4004_C070 Pin Control Register n PORTD_PCR28 32 R W 0000_0000h 11 4 1 268 4004_C07...

Страница 267: ...ter n PORTE_PCR18 32 R W 0000_0000h 11 4 1 268 4004_D04C Pin Control Register n PORTE_PCR19 32 R W 0000_0000h 11 4 1 268 4004_D050 Pin Control Register n PORTE_PCR20 32 R W 0000_0000h 11 4 1 268 4004_...

Страница 268: ...ad only field is reserved and always has the value zero 24 ISF Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes 0 Configured interrupt has not been detect...

Страница 269: ...modes 0 Low drive strength is configured on the corresponding pin if pin is configured as a digital output 1 High drive strength is configured on the corresponding pin if pin is configured as a digita...

Страница 270: ...rresponding Port Pull Enable Register bit is set 11 4 2 Global Pin Control Low Register PORTx_GPCLR Addresses PORTA_GPCLR is 4004_9000h base 80h offset 4004_9080h PORTB_GPCLR is 4004_A000h base 80h of...

Страница 271: ...to bits 15 0 of all Pin Control Registers that are enabled by the Global Pin Write Enable field provided the corresponding register has not been locked 11 4 4 Interrupt Status Flag Register PORTx_ISFR...

Страница 272: ...0C0h PORTC_DFER is 4004_B000h base C0h offset 4004_B0C0h PORTD_DFER is 4004_C000h base C0h offset 4004_C0C0h PORTE_DFER is 4004_D000h base C0h offset 4004_D0C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20...

Страница 273: ...ck source for the digital input filters Changing the filter clock source should only be done after disabling all enabled digital filters 0 Digital Filters are clocked by the bus clock 1 Digital Filter...

Страница 274: ...and individual peripherals do not override the configuration in this register for example if an I2C function is enabled on a pin then that does not override the pullup or open drain configuration for...

Страница 275: ...sensitive interrupt Rising edge sensitive interrupt Falling edge sensitive interrupt Rising and falling edge sensitive interrupt Rising edge sensitive DMA request Falling edge sensitive DMA request Ri...

Страница 276: ...ot update during stop mode The filter width in clock size is the same for all enabled digital filters within the one port and should be changed only when all digital filters for that port are disabled...

Страница 277: ...ing Clock source selection for SDHC I2S Ethernet timestamp USB and PLL FLL source System clock divide values I2S and USB clock divide values Architectural clock gating control Flash configuration USB...

Страница 278: ...can be asserted and negated at any time Assertion May occur at any time input may be asserted asynchronously to the system clock Negation May occur at any time input may be negated asynchronously to t...

Страница 279: ...k Gating Control Register 4 SIM_SCGC4 32 R W 6010_0030h 12 2 11 296 4004_8038 System Clock Gating Control Register 5 SIM_SCGC5 32 R W 0004_0180h 12 2 12 298 4004_803C System Clock Gating Control Regis...

Страница 280: ...eld descriptions Field Description 31 USBREGEN USB voltage regulator enable Controls whether the USB voltage regulator is enabled 0 USB voltage regulator is disabled 1 USB voltage regulator is enabled...

Страница 281: ...eserved and always has the value zero 15 12 RAMSIZE RAM size This field specifies the amount of system RAM available on the device 0000 Undefined 0001 Undefined 0010 Undefined 0011 Undefined 0100 Unde...

Страница 282: ...escription 31 30 Reserved This read only field is reserved and always has the value zero 29 28 SDHCSRC SDHC clock source select Selects the clock source for the SDHC clock 00 Core system clock 01 MCGP...

Страница 283: ...and always has the value zero 16 PLLFLLSEL PLL FLL clock select Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options 0 MCGFLLCLK clock 1 MCGPLLCLK clock 15 13 Reserved Thi...

Страница 284: ...l reference clock 0 System oscillator OSCCLK 1 32 kHz RTC oscillator 12 2 3 System Options Register 4 SIM_SOPT4 Address SIM_SOPT4 is 4004_7000h base 100Ch offset 4004_800Ch Bit 31 30 29 28 27 26 25 24...

Страница 285: ...FTM external clock function through the appropriate pin control register in the port control module 0 FTM_CLK0 pin 1 FTM_CLK1 pin 23 22 Reserved This read only field is reserved and always has the va...

Страница 286: ...2 Select Selects the source of FTM0 fault 2 NOTE The pin source for fault 2 must be configured for the FTM module fault function through the appropriate pin control register in the port control module...

Страница 287: ...e data 00 UART1_RX pin 01 CMP0 10 CMP1 11 Reserved 5 4 UARTTXSRC UART 1 transmit data source select Selects the source for the UART 1 transmit data 00 UART1_TX pin 01 UART1_TX pin modulated with FTM1...

Страница 288: ...le Selects how the reset pin filter is enabled See Reset pin filter for more details 000 All filtering disabled 001 Bus clock filter enabled in normal operation LPO clock filter enabled in stop mode 0...

Страница 289: ...iggers for ADC1 0 PDB trigger selected for ADC1 1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL 14 13 Reserved This read only field is reserved and always has the value zero 12 ADC1PRET...

Страница 290: ...alue zero 4 ADC0PRETRGSEL ADC0 pretrigger select Selects the ADC0 pre trigger source when alternative triggers are enabled through ADC0ALTTRGEN 0 Pre trigger A 1 Pre trigger B 3 0 ADC0TRGSEL ADC0 trig...

Страница 291: ...d and always has the value zero 15 12 REVID Device revision number Specifies the silicon implementation number for the device 11 10 Reserved This read only field is reserved and always has the value z...

Страница 292: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TRIAMP 0 OPAMP 0 UART5 UART4 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC1 f...

Страница 293: ...ys has the value zero 12 2 9 System Clock Gating Control Register 2 SIM_SCGC2 Address SIM_SCGC2 is 4004_7000h base 102Ch offset 4004_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Страница 294: ...0 RNGB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC3 field descriptions Field Description 31 Reserved This read only field is reserved and always has the value zero...

Страница 295: ...as the value zero 12 SPI2 SPI2 Clock Gate Control This bit controls the clock gate to the SPI2 module 0 Clock disabled 1 Clock enabled 11 5 Reserved This read only field is reserved and always has the...

Страница 296: ...only field is reserved and always has the value one 28 LLWU LLWU Clock Gate Control This bit controls the clock gate to the LLWU module 0 Clock disabled 1 Clock enabled 27 21 Reserved This read only...

Страница 297: ...t controls the clock gate to the UART0 module 0 Clock disabled 1 Clock enabled 9 8 Reserved This read only field is reserved and always has the value zero 7 I2C1 I2C1 Clock Gate Control This bit contr...

Страница 298: ...0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PORTE PORTD PORTC PORTB PORTA 1 0 TSI 0 REGFILE LPTIMER W Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 SIM_SCGC5 field descriptions Field Description 31 19 R...

Страница 299: ...led 8 7 Reserved This read only field is reserved and always has the value one 6 Reserved This read only field is reserved and always has the value zero 5 TSI TSI Clock Gate Control This bit controls...

Страница 300: ...ved This read only field is reserved and always has the value one 29 RTC RTC Clock Gate Control This bit controls the clock gate to the RTC module 0 Clock disabled 1 Clock enabled 28 Reserved This rea...

Страница 301: ...0 19 Reserved This read only field is reserved and always has the value zero 18 CRC CRC Clock Gate Control This bit controls the clock gate to the CRC module 0 Clock disabled 1 Clock enabled 17 16 Res...

Страница 302: ...s bit controls the clock gate to the DMA Mux module 0 Clock disabled 1 Clock enabled 0 FTFL Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory 0 Clock disabled 1 Cloc...

Страница 303: ...the device is in VLPR mode Address SIM_CLKDIV1 is 4004_7000h base 1044h offset 4004_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R OUTDIV1 OUTDIV2 OU...

Страница 304: ...by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divide by 10 1010 Divide by 11 1011 Divide by 12 1100 Divide by 13 1101 Divide by 14 1110 Divide by 15 1111 Divide by 16...

Страница 305: ...or 1111 depending on FTFL_FOPT LPBOOT 0000 Divide by 1 0001 Divide by 2 0010 Divide by 3 0011 Divide by 4 0100 Divide by 5 0101 Divide by 6 0110 Divide by 7 0111 Divide by 8 1000 Divide by 9 1001 Divi...

Страница 306: ...I2S clock divider fraction This field sets the multiply value for when the fractional clock divider is used as a the source for I2S master clock The clock input to the fractional clock divider is set...

Страница 307: ...tection region 1001 256 KB of FlexNVM 32 KB protection region 1111 256 KB of FlexNVM 32 KB protection region 27 24 PFSIZE Program flash size This field specifies the amount of program flash memory ava...

Страница 308: ...rved 15 12 Reserved This read only field is reserved and always has the value zero 11 8 DEPART FlexNVM partition For devices with FlexNVM Data flash EEPROM backup split See DEPART bit description in F...

Страница 309: ...ve 0 Swap is not active 1 Swap is active 30 Reserved This read only field is reserved and always has the value zero 29 24 MAXADDR0 Max address block 0 This field concatenated with 13 zeros indicates t...

Страница 310: ...ated with 13 zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block flash block 1 For example if MAXADDR0 MAXADDR1 0x20 the first invalid addr...

Страница 311: ...ion Unique identification for the device 12 2 21 Unique Identification Register Mid Low SIM_UIDML Address SIM_UIDML is 4004_7000h base 105Ch offset 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 1...

Страница 312: ...6 5 4 3 2 1 0 R UID W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset SIM_UIDL field descriptions Field Description 31 0 UID Unique Identification Uniq...

Страница 313: ...modes are described in this chapter Entry into each mode exit from each mode and functionality while in each of the modes are described This chapter also discusses basic information about all reset so...

Страница 314: ...M bit field can be modified to change the the MCU into the very lower power run VLPR mode when limited frequency is required during the application For the low power run mode a corresponding wait and...

Страница 315: ...from supporting peripherals are valid MCU is placed in a low leakage mode by powering down the internal logic System RAM contents retained and I O states held Internal logic states are not retained VL...

Страница 316: ...nsition From To Trigger Conditions 1 Run Wait Sleep now or sleep on exit modes entered with SLEEPDEEP clear controlled in System Control Register in ARM core Wait Run Interrupt or Reset 2 Run STOP Sle...

Страница 317: ...P 1 LPLLSM 010 Sleep now or sleep on exit modes entered with SLEEPDEEP set controlled in System Control Register in ARM core NOTE Hardware will set LPWUI and will remain set until software clears VLPS...

Страница 318: ...F_FFFF To reduce power in this mode disable unused modules by clearing the peripherals corresponding clock gating control bit in the SIM s registers 13 1 2 2 2 Very Low Power Run VLPR Mode In VLPR the...

Страница 319: ...en returning from VLPR When VLPRS is set the system is fully in VLPR mode NOTE Do not enter VLPS LLS or VLLSx until the transition to VLPR completes as indicated by the VLPRS bit Do not attempt to tra...

Страница 320: ...ode disable the clocks to unused modules by clearing the peripherals corresponding clock gating control bits in the SIM VLPR mode restrictions also apply to VLPW VLPW mode provides the option to retur...

Страница 321: ...e of providing an asynchronous interrupt to the device for example an enabled pin interrupt NMI RTC LVW UART wakeup on edge CMP or ADC takes the device out of stop mode and returns the device to norma...

Страница 322: ...n sleep now or sleep on exit mode the SLEEPDEEP bit is set in the System Control Register in the ARM core and The device is configured as per Table 13 2 In LLS the on chip voltage regulator is in stop...

Страница 323: ...is set An asserted RESET pin exits any VLLS mode This returns the device to normal run mode When exiting VLLS via the RESET pin the PIN and WAKEUP bits are set in the SRSL register 13 1 2 5 ARM Debug...

Страница 324: ...it that is set to release the ARM core being held in reset following a VLLS recovery The debugger re initializes all debug IP and then asserts the VLLDBGACK control bit to allow the Mode Controller to...

Страница 325: ...uses a reset condition As the supply voltage rises the LVD circuit holds the MCU in reset until the supply rises above the LVD low threshold VLVDL The POR and LVD bits in SRSL are set following a POR...

Страница 326: ...n and seven internal peripherals to wake the device from LLS and VLLS power modes When in VLLS mode all enabled inputs to the LLWU will generate a system reset flow when detected When in LLS mode only...

Страница 327: ...lows the chip to boot from flash memory after it has been programmed by an external source 13 1 3 10 MDM AP System Reset Request A system reset is initiated by setting the System Reset Request bit in...

Страница 328: ...ster depends on the reset type POR 0x00 LVD 0x00 Low leakage wake up LLS exit via RESET pin or any exit from VLLS 0x00 Other reset bits 2 0 are set if their corresponding reset source caused the reset...

Страница 329: ...lue of this register depends on the reset type POR 0x82 LVD 0x02 Low leakage wake up due to RESET pin assertion 0x41 Low leakage wake up due to other wake up sources 0x01 Other reset bits 6 5 and 2 ar...

Страница 330: ...Reset not caused by a loss of external clock 1 Reset caused by a loss of external clock 1 LVD Low voltage detect reset If the LVDRE bit is set and the supply drops below the LVD trip voltage an LVD re...

Страница 331: ...ad 0 AVLP ALLS 0 AVLLS3 AVLLS2 AVLLS1 Write Reset 0 0 0 0 0 0 0 0 MC_PMPROT field descriptions Field Description 7 6 Reserved This read only field is reserved and always has the value zero 5 AVLP Allo...

Страница 332: ...he MCU is configured for a disallowed power mode or to a reserved RUNM setting the device remains in its current power mode For example if in normal run RUNM 00 AVLP 0 an attempt to enter VLPR using t...

Страница 333: ...l has not been enabled using PMPROT register This field is cleared by hardware on exit from LLS or VLLS modes 00 Normal run mode 01 Reserved 10 Very low power run mode 11 Reserved 4 3 Reserved This re...

Страница 334: ...Mode Control Memory Map Register Definition K53 Sub Family Reference Manual Rev 6 Nov 2011 334 Freescale Semiconductor Inc...

Страница 335: ...nt control features include Internal voltage regulator Active POR providing brown out detect Low voltage detect protection including Multiple programmable trip voltages Warning and detect interrupt co...

Страница 336: ...1 LVD Reset Operation By setting the LVDRE bit the LVD generates a reset upon detection of a low voltage condition The low voltage detection threshold is determined by the LVDV bits After an LVD rese...

Страница 337: ...s and Control 1 Register PMC_LVDSC1 This register contains status and control bits to support the low voltage detect function This register should be written during the reset initialization program to...

Страница 338: ...LVDF 1 4 LVDRE Low Voltage Detect Reset Enable This write once bit enables LVDF events to generate a hardware reset Additional writes are ignored 0 LVDF does not generate hardware resets 1 Force an MC...

Страница 339: ...ltage warning event detected 6 LVWACK Low Voltage Warning Acknowledge This write only bit is used to acknowledge low voltage warning errors write 1 to clear LVWF Reads always return 0 5 LVWIE Low Volt...

Страница 340: ...nd always has the value zero 4 TRAMPO For devices with FlexNVM Traditional RAM Power Option For devices with program flash only Reserved For devices with FlexNVM When the FlexRAM on the device is conf...

Страница 341: ...ld Description 0 BGBE Bandgap Buffer Enable Enables the bandgap buffer 0 Bandgap buffer not enabled 1 Bandgap buffer enabled Chapter 14 Power Management Controller K53 Sub Family Reference Manual Rev...

Страница 342: ...PMC Memory Map Register Definition K53 Sub Family Reference Manual Rev 6 Nov 2011 342 Freescale Semiconductor Inc...

Страница 343: ...fore the RESET pin can be used as a low leakage reset source When in LLS mode the I O are released immediately on a wakeup or reset event In the case of LLS exit via a RESET pin the I O default to the...

Страница 344: ...on exit Wakeup exit via reset flow when MCU is in VLLS I O states remain in held state until wakeup has been acknowledged An optional digital filter provided to qualify an external pin detect and RES...

Страница 345: ...ns immediately so that if LLS or VLLS modes are entered while the the filter logic has seen an active edge on the RESET pin and is currently sensing for minimum assertion duration there is no restart...

Страница 346: ...upt module flag detect Reset filter Edge detect Edge detect LLS VLLS entered Module6 interrupt flag LLWU_M6IF WUME6 LLWU_MWUF6 occurred Interrupt module flag detect System Error Figure 15 1 LLWU block...

Страница 347: ...4007_C001 LLWU Pin Enable 2 Register LLWU_PE2 8 R W 00h 15 3 2 348 4007_C002 LLWU Pin Enable 3 Register LLWU_PE3 8 R W 00h 15 3 3 350 4007_C003 LLWU Pin Enable 4 Register LLWU_PE4 8 R W 00h 15 3 4 35...

Страница 348: ...ternal input pin enabled with any change detection 3 2 WUPE1 Wakeup Pin Enable for LLWU_P1 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 0...

Страница 349: ...s wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input pin enabled with any change detection 3 2 WUPE5 Wake...

Страница 350: ...4 WUPE10 Wakeup Pin Enable for LLWU_P10 Enables and configures the edge detection for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detec...

Страница 351: ...for the wakeup pin 00 External input pin disabled as wakeup input 01 External input pin enabled with rising edge detection 10 External input pin enabled with falling edge detection 11 External input...

Страница 352: ...from low leakage modes exit from LLS via RESET or any exit from VLLS Address LLWU_ME is 4007_C000h base 4h offset 4007_C004h Bit 7 6 5 4 3 2 1 0 Read WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 W...

Страница 353: ...rce input 0 Internal module flag not used as wakeup source 1 Internal module flag used as wakeup source 0 WUME0 Wakeup Module Enable for Module 0 Enables an internal module as a wakeup source input 0...

Страница 354: ...e a one to WUF5 0 LLWU_P5 input was not a source of wakeup from LLS or VLLS mode 1 LLWU_P5 input was a source of wakeup from LLS or VLLS mode 4 WUF4 Wakeup Flag for LLWU_P4 Indicates that an enabled e...

Страница 355: ...l be the source causing the CPU interrupt flow For VLLS this will be the source causing the MCU reset flow The external wakeup flags are read only and clearing a flag is accomplished by a write of a o...

Страница 356: ...3 WUF11 Wakeup Flag for LLWU_P11 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS To clear the flag write a one to WUF11 0 LLWU_P11 input was not a source of wakeup f...

Страница 357: ...when LLS or VLLS was entered An immediate wakeup event was triggered and the source of the wakeup event is not known Error handling routines should treat this source as an unknown wakeup To clear the...

Страница 358: ...le 2 input was a source of wakeup from LLS or VLLS mode 1 MWUF1 Wakeup flag for module 1 Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS To clear the flag follow the...

Страница 359: ...al Pin Enables the digital filter for the external pin detect 0 Filter not enabled 1 Filter enabled 0 FLTR Digital Filter on RESET Pin Enables the digital filter for the RESET pin during LLS and VLLS...

Страница 360: ...state retention mode where all registers and memory retains its contents The I O pins are held in their input or output state Upon wakeup the power management control PMC is re enabled goes through a...

Страница 361: ...power mode recovery Recovery from VLLSx is through the wake up Reset event The chip wake ups from VLLSx by means of reset an enabled pin or enabled module See the table LLWU inputs in the LLWU configu...

Страница 362: ...Functional description K53 Sub Family Reference Manual Rev 6 Nov 2011 362 Freescale Semiconductor Inc...

Страница 363: ...visible information on the platform configuration and revision Control and counting logic for ETB almost full 16 2 Memory Map Register Descriptions The memory map and register descriptions below desc...

Страница 364: ...M_PLASC is E008_0000h base 8h offset E008_0008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 MCM_PLASC field descriptions Field Description 15 8 Res...

Страница 365: ...00Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SRAMLWP SRAMLAP 0 SRAMUWP SRAMUAP Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Res...

Страница 366: ...he processor 10 Fixed priority Processor has highest backdoor has lowest 11 Fixed priority Backdoor has highest processor has lowest 23 9 Reserved This field is reserved 8 0 Reserved This field is res...

Страница 367: ...IS ETDIS RLRQ RSPT CNTEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ETBCC field descriptions Field Description 31 6 Reserved This read only field is reserved and alway...

Страница 368: ...ETB counter 0 ETB counter disabled 1 ETB counter enabled 16 2 6 ETB reload register MCM_ETBRL Address MCM_ETBRL is E008_0000h base 18h offset E008_0018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Страница 369: ...ter value Indicates the current 0 mod 4 value of the counter 16 3 Functional Description This section describes the functional description of MCM module 16 3 1 Interrupts The MCM generates two interru...

Страница 370: ...true MCM_ISCR ETBI is set which is caused by The ETB counter is enabled MCM_ETBCC CNTEN 1 The ETB count expires and The response to counter expiration is a normal interrupt MCM_ETBCC RSPT 01 Function...

Страница 371: ...bitration among the bus masters when they access the same slave A variety of bus arbitration methods and attributes may be programmed on a slave by slave basis 17 1 1 Features The crossbar switch incl...

Страница 372: ...ion details for the exact master slave assignments for your device AXBS memory map Absolute address hex Register name Width in bits Access Reset value Section page 4000_4000 Priority Registers Slave A...

Страница 373: ...0000_0000h 17 2 3 378 4000_4E00 Master General Purpose Control Register AXBS_MGPCR6 32 R W 0000_0000h 17 2 3 378 4000_4F00 Master General Purpose Control Register AXBS_MGPCR7 32 R W 0000_0000h 17 2 3...

Страница 374: ...y when accessing the slave port 010 This master has level 3 priority when accessing the slave port 011 This master has level 4 priority when accessing the slave port 100 This master has level 5 priori...

Страница 375: ...sing the slave port 15 Reserved This read only field is reserved and always has the value zero 14 12 M3 Master 3 priority Sets the arbitration priority for this port on the associated slave port 000 T...

Страница 376: ...essing the slave port 011 This master has level 4 priority when accessing the slave port 100 This master has level 5 priority when accessing the slave port 101 This master has level 6 priority when ac...

Страница 377: ...s reserved and always has the value zero 5 4 PCTL Parking control Determines the slave port s parking control The low power park feature results in an overall power savings if the slave port is not sa...

Страница 378: ...0_4000h base E00h offset 4000_4E00h AXBS_MGPCR7 is 4000_4000h base F00h offset 4000_4F00h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 AULB W Reset 0 0...

Страница 379: ...ontrol of the targeted slave port only after a previous access to a different slave port completes regardless of its priority on the newly targeted slave port This prevents deadlock from occurring whe...

Страница 380: ...ster accesses but instead track only with slave accesses The MGPCRx AULB bits are the exception to this rule The update of these bits is only recognized when the master on that master port runs an IDL...

Страница 381: ...e master has run four more beats of its burst After the fourth beat of the now continued burst or the ninth beat of the second burst from the master s perspective is taken all beats of the burst are o...

Страница 382: ...ter s priority level is lower than the current master At the conclusion of one of the following cycles An IDLE cycle A non IDLE cycle to a location other than the current slave port 17 3 3 3 Round rob...

Страница 383: ...que 3 bit priority level If an attempt is made to program multiple master ports with the same priority level within the priority registers PRSn the crossbar switch responds with a bus error and the re...

Страница 384: ...Initialization application information K53 Sub Family Reference Manual Rev 6 Nov 2011 384 Freescale Semiconductor Inc...

Страница 385: ...cient rights are terminated with a protection error response 18 2 1 Block Diagram A simplified block diagram of the MPU module is shown in the following figure The hardware s two dimensional connectio...

Страница 386: ...nerated by each bus master in the system The feature set includes 12 program visible 128 bit region descriptors accessible by four 32 bit words each Each region descriptor defines a modulo 32 byte spa...

Страница 387: ...only be referenced using 32 bit accesses Attempted references using different access sizes to undefined reserved addresses or with a non supported access type a write to a read only register or a rea...

Страница 388: ...RGD2_WORD1 32 R W 0000_001Fh 18 3 5 395 4000_D428 Region Descriptor n Word 2 MPU_RGD2_WORD2 32 R W 0000_0000h 18 3 6 395 4000_D42C Region Descriptor n Word 3 MPU_RGD2_WORD3 32 R W 0000_0000h 18 3 7 39...

Страница 389: ...0000_0000h 18 3 4 394 4000_D4A4 Region Descriptor n Word 1 MPU_RGD10_WORD1 32 R W 0000_001Fh 18 3 5 395 4000_D4A8 Region Descriptor n Word 2 MPU_RGD10_WORD2 32 R W 0000_0000h 18 3 6 395 4000_D4AC Reg...

Страница 390: ...0 0 0 0 0 1 MPU_CESR field descriptions Field Description 31 27 SPERR Slave port n error Indicates a captured error in EARn and EDRn This bit is set when the hardware detects an error and records the...

Страница 391: ...he number of slave ports connected to the MPU 11 8 NRGD Number of region descriptors Indicates the number of region descriptors implemented in the MPU 0000 8 region descriptors 0001 12 region descript...

Страница 392: ...iolation Addresses MPU_EAR0 is 4000_D000h base 10h offset 4000_D010h MPU_EAR1 is 4000_D000h base 18h offset 4000_D018h MPU_EAR2 is 4000_D000h base 20h offset 4000_D020h MPU_EAR3 is 4000_D000h base 28h...

Страница 393: ...18 17 16 R EACD W Reset x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 EMN EATTR ERW W Reset x x x x x x x x x x x x x x x x Notes x Undefined at reset MPU_EDRn field d...

Страница 394: ...tes to this register clear the region descriptor s valid bit RGDn_WORD3 VLD Addresses 4000_D000h base 400h offset 16d n where n 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1...

Страница 395: ...served This field is reserved 18 3 6 Region Descriptor n Word 2 MPU_RGD_WORD2 The third word of the region descriptor defines the access control rights of the memory region The access control privileg...

Страница 396: ...rformed 1 Bus master 7 reads allowed 30 M7WE Bus master 7 write enable 0 Bus master 7 writes terminate with an access error and the write is not performed 1 Bus master 7 writes allowed 29 M6RE Bus mas...

Страница 397: ...ndent bits enabling read r write w and execute x permissions 0 An attempted access of that mode may be terminated with an access error if not allowed by another descriptor and the access not performed...

Страница 398: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 VLD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD3 field descriptions Field Description 31 1 Reserved This r...

Страница 399: ...escription 31 M7RE Bus master 7 read enable 0 Bus master 7 reads terminate with an access error and the read is not performed 1 Bus master 7 reads allowed 30 M7WE Bus master 7 write enable 0 Bus maste...

Страница 400: ...20 18 M3UM Bus master 3 user mode access control Defines the access controls for bus master 3 in user mode M3UM consists of three independent bits enabling read r write w and execute x permissions 0 A...

Страница 401: ...n the access evaluation macro a hardware structure replicated in the two dimensional connection matrix As shown in the following figure the access evaluation macro inputs the crossbar bus address phas...

Страница 402: ...g the master and supervisor user mode signals a set of effective permissions is generated from the appropriate fields in the region descriptor The protection violation logic then evaluates the access...

Страница 403: ...ng the MPU by clearing CESR VLD minimizes power dissipation To minimize the power dissipation of an enabled MPU invalidate unused region descriptors by clearing the associated RGDn_Word3 VLD bits 18 5...

Страница 404: ...n and EDRn capture information on the faulting reference The error terminated bus cycle typically initiates an error response in the originating bus master For example a processor core may respond wit...

Страница 405: ...1 and the access controls are defined by the logical OR of the two region descriptors Thus CP0 has rw r rw permissions while CP1 has r r permission in this space Both DMA engines are excluded from thi...

Страница 406: ...Application Information K53 Sub Family Reference Manual Rev 6 Nov 2011 406 Freescale Semiconductor Inc...

Страница 407: ...er peripherals 19 1 1 Features Key features of the peripheral bridge are Supports up to 128 peripherals Supports 8 16 and 32 bit width peripheral slots Each independently configurable peripheral inclu...

Страница 408: ...pped into the PACR0 address space Two system clocks are required for read accesses and three system clocks are required for write accesses to the peripheral bridge registers NOTE The number of fields...

Страница 409: ...2 2 413 4008_0028 Peripheral Access Control Register AIPS1_PACRC 32 R W 4444_4444h 19 2 2 413 4008_002C Peripheral Access Control Register AIPS1_PACRD 32 R W 4444_4444h 19 2 2 413 4008_0040 Peripheral...

Страница 410: ...5 MTW5 MPL5 0 0 W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset AIPSx_MPRA field descriptions Field Description 31 Reserved This read only field is r...

Страница 411: ...cesses 0 This master is not trusted for read accesses 1 This master is trusted for read accesses 21 MTW2 Master trusted for writes Determines whether the master is trusted for write accesses 0 This ma...

Страница 412: ...cifies how the privilege level of the master is determined 0 Accesses from this master are forced to user mode 1 Accesses from this master are not forced to user mode 11 Reserved This read only field...

Страница 413: ...11 8 7 4 3 0 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PA...

Страница 414: ...ed This read only field is reserved and always has the value zero 30 SP0 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access When this bit is set the ma...

Страница 415: ...tes 0 Accesses from an untrusted master are allowed 1 Accesses from an untrusted master are not allowed 23 Reserved This read only field is reserved and always has the value zero 22 SP2 Supervisor pro...

Страница 416: ...an untrusted master When this bit is set and an access is attempted by an untrusted master the access terminates with an error response and no peripheral access initiates 0 Accesses from an untrusted...

Страница 417: ...cesses 1 This peripheral is write protected 8 TP5 Trusted protect Determines whether the peripheral allows accesses from an untrusted master When this bit is set and an access is attempted by an untru...

Страница 418: ...the peripheral allows write accesss When this bit is set and a write access is attempted access terminates with an error response and no peripheral access initiates 0 This peripheral allows write acce...

Страница 419: ...lege level for accesses 29 WP0 Write protect Determines whether the peripheral allows write accesss When this bit is set and a write access is attempted access terminates with an error response and no...

Страница 420: ...for the master must be set If not access terminates with an error response and no peripheral access initiates 0 This peripheral does not require supervisor privilege level for accesses 1 This periphe...

Страница 421: ...or privilege level for access When this bit is set the master privilege level must indicate the supervisor access attribute and the MPROTn MPL control bit for the master must be set If not access term...

Страница 422: ...eld is reserved and always has the value zero 6 SP6 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access When this bit is set the master privilege level...

Страница 423: ...with an error response and no peripheral access initiates 0 Accesses from an untrusted master are allowed 1 Accesses from an untrusted master are not allowed 19 3 Functional Description The peripheral...

Страница 424: ...Functional Description K53 Sub Family Reference Manual Rev 6 Nov 2011 424 Freescale Semiconductor Inc...

Страница 425: ...on details of this module s instances see the chip configuration chapter 20 1 1 Overview The DMA Mux routes up to 63 DMA sources called slots to be mapped to any of the 16 DMA channels This is illustr...

Страница 426: ...on slots can be routed to 16 channels 16 independently selectable DMA channel routers The first 4 channels additionally provide a trigger functionality Each channel router can be assigned to one of th...

Страница 427: ...or a receive buffer becomes full periodically Configuration of the period is done in the registers of the periodic interrupt timer PIT This mode is only available for channels 0 3 20 2 External signa...

Страница 428: ...on Register DMAMUX_CHCFG10 8 R W 00h 20 3 1 428 4002_100B Channel Configuration Register DMAMUX_CHCFG11 8 R W 00h 20 3 1 428 4002_100C Channel Configuration Register DMAMUX_CHCFG12 8 R W 00h 20 3 1 42...

Страница 429: ...al description of the DMA MUX The primary purpose of the DMA MUX is to provide flexibility in the system s use of the available DMA channels As such configuration of the DMA MUX is intended to be a st...

Страница 430: ...teed DMA Channel 0 Trigger 2 Source 1 Source 2 Source 3 Always 1 DMA Channel 3 Always y Trigger 4 Source x Trigger 1 DMA Channel 1 Figure 20 19 DMA MUX triggered channels The DMA channel triggering ca...

Страница 431: ...rs presumably from memory as long as its transmit buffer is empty By using a trigger on this channel the SPI transfers can be automatically performed every 5 s as an example On the receive side of the...

Страница 432: ...e external bus or vice versa Similar to memory to memory transfers this is typically done as quickly as possible Any DMA transfer that requires software activation Any DMA transfer that should be expl...

Страница 433: ...or initializing the DMA channel MUX 20 5 1 Reset The reset state of each individual bit is shown in Memory map register definition In summary after reset all channels are disabled and must be explicit...

Страница 434: ...igned char DMAMUX_BASE_ADDR 0x000D volatile unsigned char CHCONFIG14 volatile unsigned char DMAMUX_BASE_ADDR 0x000E volatile unsigned char CHCONFIG15 volatile unsigned char DMAMUX_BASE_ADDR 0x000F In...

Страница 435: ...nnel for the new source 2 Clear the CHCFG ENBL and CHCFG TRIG bits of the DMA channel 3 Select the source to be routed to the DMA channel Write to the corresponding CHCFG register ensuring that the CH...

Страница 436: ...0x000B volatile unsigned char CHCONFIG12 volatile unsigned char DMAMUX_BASE_ADDR 0x000C volatile unsigned char CHCONFIG13 volatile unsigned char DMAMUX_BASE_ADDR 0x000D volatile unsigned char CHCONFI...

Страница 437: ...ule capable of performing complex data transfers with minimal intervention from a host processor The hardware microarchitecture includes A DMA engine that performs Source and destination address calcu...

Страница 438: ...ata Write Address Internal Peripheral Bus eDMA Peripheral Request eDMA Done Figure 21 1 eDMA block diagram 21 1 2 Block parts The eDMA module is partitioned into two major modules the eDMA engine and...

Страница 439: ...master read write datapath It includes 16 bytes of register storage and the necessary multiplex logic to support any required data alignment The internal read data bus is the primary input and the in...

Страница 440: ...om source write to destination Programmable source and destination addresses and transfer size Support for enhanced addressing modes 16 channel implementation that performs complex data transfers with...

Страница 441: ...service request initiates a transfer of a specific number of bytes NBYTES as specified in the transfer control descriptor TCD The minor loop is the sequence of read write operations that transfers th...

Страница 442: ...l Register DMA_CR 32 R W 0000_0000h 21 3 1 456 4000_8004 Error Status Register DMA_ES 32 R 0000_0000h 21 3 2 458 4000_800C Enable Request Register DMA_ERQ 32 R W 0000_0000h 21 3 3 460 4000_8014 Enable...

Страница 443: ...I0 8 R W Undefined 21 3 16 478 4000_8104 Channel n Priority Register DMA_DCHPRI7 8 R W Undefined 21 3 16 478 4000_8105 Channel n Priority Register DMA_DCHPRI6 8 R W Undefined 21 3 16 478 4000_8106 Cha...

Страница 444: ...ess DMA_TCD0_DADDR 32 R W Undefined 21 3 24 484 4000_9014 TCD Signed Destination Address Offset DMA_TCD0_DOFF 16 R W Undefined 21 3 25 485 4000_9016 TCD Current Minor Loop Link Major Loop Count Channe...

Страница 445: ...Control and Status DMA_TCD1_CSR 16 R W Undefined 21 3 29 488 4000_903E TCD Beginning Minor Loop Link Major Loop Count Channel Linking Enabled DMA_TCD1_BITER_ELINKYES 16 R W Undefined 21 3 30 490 4000_...

Страница 446: ..._9066 TCD Transfer Attributes DMA_TCD3_ATTR 16 R W Undefined 21 3 19 480 4000_9068 TCD Minor Byte Count Minor Loop Disabled DMA_TCD3_NBYTES_MLNO 32 R W Undefined 21 3 20 481 4000_9068 TCD Signed Minor...

Страница 447: ...Adjustment DMA_TCD4_SLAST 32 R W Undefined 21 3 23 484 4000_9090 TCD Destination Address DMA_TCD4_DADDR 32 R W Undefined 21 3 24 484 4000_9094 TCD Signed Destination Address Offset DMA_TCD4_DOFF 16 R...

Страница 448: ...t Scatter Gather Address DMA_TCD5_DLASTSGA 32 R W Undefined 21 3 28 487 4000_90BC TCD Control and Status DMA_TCD5_CSR 16 R W Undefined 21 3 29 488 4000_90BE TCD Beginning Minor Loop Link Major Loop Co...

Страница 449: ...ource Address Offset DMA_TCD7_SOFF 16 R W Undefined 21 3 18 480 4000_90E6 TCD Transfer Attributes DMA_TCD7_ATTR 16 R W Undefined 21 3 19 480 4000_90E8 TCD Minor Byte Count Minor Loop Disabled DMA_TCD7...

Страница 450: ...DMA_TCD8_NBYTES_MLOFFYES 32 R W Undefined 21 3 22 483 4000_910C TCD Last Source Address Adjustment DMA_TCD8_SLAST 32 R W Undefined 21 3 23 484 4000_9110 TCD Destination Address DMA_TCD8_DADDR 32 R W...

Страница 451: ...6 R W Undefined 21 3 27 486 4000_9138 TCD Last Destination Address Adjustment Scatter Gather Address DMA_TCD9_DLASTSGA 32 R W Undefined 21 3 28 487 4000_913C TCD Control and Status DMA_TCD9_CSR 16 R W...

Страница 452: ...ined 21 3 31 491 4000_9160 TCD Source Address DMA_TCD11_SADDR 32 R W Undefined 21 3 17 479 4000_9164 TCD Signed Source Address Offset DMA_TCD11_SOFF 16 R W Undefined 21 3 18 480 4000_9166 TCD Transfer...

Страница 453: ...efined 21 3 21 482 4000_9188 TCD Signed Minor Loop Offset Minor Loop and Offset Enabled DMA_TCD12_NBYTES_MLOFFYES 32 R W Undefined 21 3 22 483 4000_918C TCD Last Source Address Adjustment DMA_TCD12_SL...

Страница 454: ...annel Linking Enabled DMA_TCD13_CITER_ELINKYES 16 R W Undefined 21 3 26 485 4000_91B6 DMA_TCD13_CITER_ELINKNO 16 R W Undefined 21 3 27 486 4000_91B8 TCD Last Destination Address Adjustment Scatter Gat...

Страница 455: ...p Link Major Loop Count Channel Linking Disabled DMA_TCD14_BITER_ELINKNO 16 R W Undefined 21 3 31 491 4000_91E0 TCD Source Address DMA_TCD15_SADDR 32 R W Undefined 21 3 17 479 4000_91E4 TCD Signed Sou...

Страница 456: ...e For fixed priority arbitration the highest priority channel requesting service is selected to execute The channel priority registers assign the priorities see the DCHPRIn registers For round robin a...

Страница 457: ...low the minor loop offset to be applied to the source address the destination address or both The NBYTES field is reduced when either offset is enabled 6 CLM Continuous Link Mode 0 A minor loop channe...

Страница 458: ...le See the Error Reporting and Handling section for more details Address DMA_ES is 4000_8000h base 4h offset 4000_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R VLD 0 ECX W Reset 0 0 0 0...

Страница 459: ...ess configuration error 1 The last recorded error was a configuration error detected in the TCDn_DADDR field TCDn_DADDR is inconsistent with TCDn_ATTR DSIZE 4 DOE Destination Offset Error 0 No destina...

Страница 460: ...accepted The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request Address DMA_ERQ is 4000_8000h base Ch offset 40...

Страница 461: ...uest signal for the corresponding channel is disabled 1 The DMA request signal for the corresponding channel is enabled 7 ERQ7 Enable DMA Request 7 0 The DMA request signal for the corresponding chann...

Страница 462: ...register The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller Address DMA_EEI is...

Страница 463: ...channel does not generate an error interrupt 1 The assertion of the error signal for corresponding channel generates an error interrupt request 7 EEI7 Enable Error Interrupt 7 0 The error signal for c...

Страница 464: ...ble the error interrupt for a given channel The data value on a register write causes the corresponding bit in the EEI to be cleared Setting the CAEE bit provides a global clear function forcing the E...

Страница 465: ...a 32 bit word Reads of this register return all zeroes Address DMA_SEEI is 4000_8000h base 19h offset 4000_8019h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAEE 0 SEEI Reset 0 0 0 0 0 0 0 0 DMA_SEEI fie...

Страница 466: ...te multiple byte registers as a 32 bit word Reads of this register return all zeroes Address DMA_CERQ is 4000_8000h base 1Ah offset 4000_801Ah Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAER 0 CERQ Rese...

Страница 467: ...as a 32 bit word Reads of this register return all zeroes Address DMA_SERQ is 4000_8000h base 1Bh offset 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ...

Страница 468: ...a 32 bit word Reads of this register return all zeroes Address DMA_CDNE is 4000_8000h base 1Ch offset 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE fi...

Страница 469: ...this register return all zeroes Address DMA_SSRT is 4000_8000h base 1Dh offset 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field D...

Страница 470: ...e multiple byte registers as a 32 bit word Reads of this register return all zeroes Address DMA_CERR is 4000_8000h base 1Eh offset 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset...

Страница 471: ...n this register 6 CAIR Clear All Interrupt Requests 0 Clear only the INT bit specified in the CINT field 1 Clear all bits in INT 5 4 Reserved This field is reserved 3 0 CINT Clear Interrupt Request Cl...

Страница 472: ...w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_INT field descriptions Field Description 31 16 Reserved This read only field is reserved and a...

Страница 473: ...terrupt request for corresponding channel is active 5 INT5 Interrupt Request 5 0 The interrupt request for corresponding channel is cleared 1 The interrupt request for corresponding channel is active...

Страница 474: ...a channel error regardless of the state of the EEI The state of any given channel s error indicators is affected by writes to this register it is also affected by writes to the CERR On writes to the...

Страница 475: ...0 0 An error in the corresponding channel has not occurred 1 An error in the corresponding channel has occurred 9 ERR9 Error In Channel 9 0 An error in the corresponding channel has not occurred 1 An...

Страница 476: ...est Status Register DMA_HRS The HRS provides a bit map for the DMA channels signaling the presence of a hardware request for each channel The hardware request status bits reflect the current state of...

Страница 477: ...S10 Hardware Request Status Channel 10 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 9 HRS9 Hardware R...

Страница 478: ...0 0 A hardware service request for the corresponding channel is not present 1 A hardware service request for the corresponding channel is present 21 3 16 Channel n Priority Register DMA_DCHPRIn When f...

Страница 479: ...arbitration is enabled NOTE Reset value for the channel priority fields CHPRI is equal to the corresponding channel number for each priority register i e DCHPRI15 CHPRI equals 0b1111 21 3 17 TCD Sour...

Страница 480: ...OD Source Address Modulo 0 Source address modulo feature is disabled 0 This value defines a specific address range specified to be the value after SADDR SOFF calculation is performed or the original r...

Страница 481: ...TCD word 2 s register definition Addresses 4000_8000h base 1008h offset 32d n where n 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NBYTES W Res...

Страница 482: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SMLOE DMLOE NBYTES W Reset x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_NBYTES_MLOFFNO...

Страница 483: ...esses 4000_8000h base 1008h offset 32d n where n 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SMLOE DMLOE MLOFF NBYTES W Reset x x x x x x x x...

Страница 484: ...Addresses 4000_8000h base 100Ch offset 32d n where n 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SLAST W Reset x x x x x x x x x x x x x x x x...

Страница 485: ...ress Signed offset Sign extended offset applied to the current destination address to form the next state value as each destination write is completed 21 3 26 TCD Current Minor Loop Link Major Loop Co...

Страница 486: ...el s TCDn_CSR START bit 8 0 CITER Current Major Iteration Count This 9 bit ELINK 1 or 15 bit ELINK 0 count represents the current major loop count for the channel It is decremented each time the minor...

Страница 487: ...calculations optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count BITER field NOTE When the CITER field is initially loa...

Страница 488: ...In general as the eDMA processes the minor loop it continuously generates read write sequences until the minor count is exhausted This field forces the eDMA to stall after the completion of each read...

Страница 489: ...essing in the current channel If enabled the eDMA engine uses DLASTSGA as a memory pointer to a 0 modulo 32 address containing a 32 byte data structure loaded as the transfer control descriptor into t...

Страница 490: ...ffset 32d n where n 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ELINK 0 LINKCH BITER Write Reset x x x x x x x x x x x x x x x x Notes x Undefined at reset DMA_TCDn_BITER_ELINKYES field d...

Страница 491: ...d must be set equal to the corresponding CITER field Otherwise a configuration error is reported As the major iteration count is exhausted the contents of this field is reloaded into the CITER field I...

Страница 492: ...e this 9 bit ELINK 1 or 15 bit ELINK 0 field must be equal to the value in the CITER field As the major iteration count is exhausted the contents of this field are reloaded into the CITER field NOTE W...

Страница 493: ...odule then into the program model and channel arbitration In the next cycle the channel arbitration performs using the fixed priority or round robin algorithm After arbitration is complete the activat...

Страница 494: ...write processing continues until the minor byte count has transferred After the minor byte count has moved the final phase of the basic data flow is performed In this segment the address path logic p...

Страница 495: ...control descriptor or an illegal priority register setting in Fixed Arbitration mode or An error termination to a bus master read or write cycle A configuration error is reported when the starting so...

Страница 496: ...ead or write transaction which is already pipelined after errant access has completed If a bus error occurs on the last read prior to beginning the write sequence the write executes using the data cap...

Страница 497: ...el is not supported After a preempting channel begins execution it cannot be preempted Preemption is available only when fixed arbitration is selected A channel s ability to preempt another channel ca...

Страница 498: ...b internal peripheral bus 66 7 MHz 32b 133 3 66 7 53 3 83 3 MHz 32b 166 7 83 3 66 7 100 0 MHz 32b 200 0 100 0 80 0 133 3 MHz 32b 266 7 133 3 106 7 150 0 MHz 32b 300 0 150 0 120 0 Internal SRAM to inte...

Страница 499: ...accesses In the case of an internal peripheral bus read and internal SRAM write the combined data phase time is 4 cycles For an SRAM read and internal peripheral bus write it is 5 cycles Table 21 294...

Страница 500: ...the time from Cycle 4 to Cycle 5 The resulting peak request rate as a function of the system frequency is shown in the following table Table 21 295 eDMA peak request rate MReq sec System frequency MHz...

Страница 501: ...rite zero wait states on the system bus from a cold start where no channel is executing and eDMA is idle are 11 cycles for a software that is a TCDn_CSR START bit request 12 cycles for a hardware that...

Страница 502: ...he arbitration and priority levels written into the programmer s model The eDMA engine reads the entire TCD including the TCD control and status fields as shown in the following table for the selected...

Страница 503: ...terrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes The following figure shows how each DMA request initiates one minor loop transfer or iteratio...

Страница 504: ...exception of channel priority error ES CPE For all error types other than channel priority error the channel number causing the error is recorded in the ES register If the error source is not removed...

Страница 505: ...as a byte wide memory port located at 0x1000 The destination memory has a 32 bit port located at 0x2000 The address offsets are programmed in increments to match the transfer size one byte for the sou...

Страница 506: ...teration of the minor loop major loop complete 6 The eDMA engine writes TCDn_SADDR 0x1000 TCDn_DADDR 0x2000 TCDn_CITER 1 TCDn_BITER 7 The eDMA engine writes TCDn_CSR ACTIVE 0 TCDn_CSR DONE 1 INT n 1 8...

Страница 507: ...n of the minor loop g Read byte from location 0x100C read byte from location 0x100D read byte from 0x100E read byte from 0x100F h Write 32 bits to location 0x200C last iteration of the minor loop 6 eD...

Страница 508: ...odulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2 MOD is a 5 bit field for the source and destination...

Страница 509: ...because the active status may be missed if the channel execution is short in duration The TCD status bits execute the following sequence for a software activated channel Stage TCDn_CSR bits State STAR...

Страница 510: ...sses can give an indication of the progress of the transfer All other values are read back from the TCD local memory 21 5 5 3 Checking channel preemption status Preemption is available only when fixed...

Страница 511: ...executes as 1 Minor loop done set TCD12_CSR START bit 2 Minor loop done set TCD12_CSR START bit 3 Minor loop done set TCD12_CSR START bit 4 Minor loop done major loop done set TCD7_CSR START bit When...

Страница 512: ...te channels 21 5 7 2 Dynamically changing the channel linking and scatter gather options Dynamic channel linking and dynamic scatter gather is the process of changing the TCDn_CSR MAJOR_E_LINK or TCDn...

Страница 513: ...amic requests the TCD local memory controller forces the TCDn_CSR MAJOR_E_LINK and TCDn_CSR E_SG bits to zero on any writes to a TCDn after the TCDn_CSR DONE bit for that channel is set indicating tha...

Страница 514: ...Initialization application information K53 Sub Family Reference Manual Rev 6 Nov 2011 514 Freescale Semiconductor Inc...

Страница 515: ...stem External Watchdog Monitor EWM is designed to monitor external circuits as well as the MCU software flow This provides a back up mechanism to the internal watchdog that resets the MCU s CPU and pe...

Страница 516: ...the EWM s counter freezes There are two possible ways to exit from Stop mode On exit from stop mode through a reset the EWM remains disabled On exit from stop mode by an interrupt the EWM is re enabl...

Страница 517: ...ntry of debug mode it remains disabled 22 1 3 Block Diagram This figure shows the EWM block diagram Clock Gating Cell EWM_out EWM Out Logic EWM_out OR Low Power Clock Enable Counter Overflow CPU Reset...

Страница 518: ...ry map Absolute address hex Register name Width in bits Access Reset value Section page 4006_1000 Control Register EWM_CTRL 8 R W 00h 22 3 1 518 4006_1001 Service Register EWM_SERV 8 W always reads ze...

Страница 519: ...ure of this bit 22 3 2 Service Register EWM_SERV The SERV register provides the interface from the CPU to the EWM module It is write only and reads of this register return zero Address EWM_SERV is 400...

Страница 520: ...CPU reset even if the default minimum service time is required 22 3 4 Compare High Register EWM_CMPH The CMPH register is reset to 0xFF after a CPU reset This provides a maximum of 256 clocks time fo...

Страница 521: ...cuted as expected The EWM_out signal is asserted in any of the following conditions Servicing the EWM when the counter value is less than CMPL value If the EWM counter value reaches the CMPH value and...

Страница 522: ...hat the EWM_out stays in the deasserted state otherwise the EWM_out pin is asserted Note You must update the CMPH and CMPL registers prior to enabling the EWM After enabling the EWM the counter resets...

Страница 523: ...ee possible conditions can occur Table 22 7 EWM Refresh Mechanisms Condition Mechanism A unique EWM service occurs when CMPL Counter CMPH The software behaves as expected and the counter of the EWM is...

Страница 524: ...Functional Description K53 Sub Family Reference Manual Rev 6 Nov 2011 524 Freescale Semiconductor Inc...

Страница 525: ...n The watchdog monitors the operation of the system by expecting periodic communication from the software generally known as servicing or refreshing the watchdog If this periodic refreshing does not o...

Страница 526: ...hat WDOG timer is operational NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value Windowed refresh option Provides robust chec...

Страница 527: ...ck Osc WDOG Clock Selection WDOG CLK R System reset and SRS register Interrupt IRQ_RST_ EN 1 Invalid Unlock Seq 32 bit Timer Timer Time out Refresh Outside Window Invalid Refresh Seq No config after u...

Страница 528: ...so switch over to an alternate clock source if required through a control register bit 23 3 1 Unlocking and Updating the Watchdog You can unlock the write once only control and configuration registers...

Страница 529: ...d to update them only within a period of 256 bus clock cycles after unlocking This window period is known as the watchdog configuration time WCT In addition these register bits can be modified only on...

Страница 530: ...4 Windowed Mode of Operation In this mode of operation a restriction is placed on the point in time within the time out period at which the watchdog can be refreshed The refresh is considered valid on...

Страница 531: ...lso not increment In Power down mode the watchdog is powered off 23 3 7 Debug Modes of Operation You can program the watchdog to disable in debug modes through DBG_EN bit in the watchdog control regis...

Страница 532: ...les the test mode permanently until reset For running a particular test first select that test Thereafter set a certain test mode bit to put the watchdog in the functional test mode Setting this bit a...

Страница 533: ...s an overflow signal The overflow signal acts as an enable to the N 1th stage In the test mode when an individual byte N is tested byte N 1 is loaded forcefully with 0xFF and both these bytes are allo...

Страница 534: ...p reset generator routing out the time out signal as a reset to the system 23 6 Generated Resets and Interrupts The watchdog generates a reset on the following events referred to as exceptions at some...

Страница 535: ...terrupt service routine execution Also the jobs like counting the number of watchdog resets would not be done 23 7 Memory Map and Register Definition This section consists of the memory map and regist...

Страница 536: ...TOPEN DBGEN ALLOWUPDATE WINEN IRQRSTEN CLKSRC WDOGEN Write Reset 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 WDOG_STCTRLH field descriptions Field Description 15 Reserved This read only field is reserved and alwa...

Страница 537: ...ed in CPU stop mode 5 DBGEN Enables or disables WDOG in Debug mode 0 WDOG is disabled in CPU Debug mode 1 WDOG is enabled in CPU Debug mode 4 ALLOWUPDATE Enables updates to watchdog write once registe...

Страница 538: ...llowed by a reset WCT time later The interrupt can be cleared by writing 1 to this bit It also gets cleared on a system reset 14 0 Reserved This field is reserved NOTE Do not modify this bitfield valu...

Страница 539: ...w Register High WDOG_WINH You must set the Window Register value lower than the Time out Value Register Address WDOG_WINH is 4005_2000h base 8h offset 4005_2008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Страница 540: ...dog Refresh Register WDOG_REFRESH Address WDOG_REFRESH is 4005_2000h base Ch offset 4005_200Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGREFRESH Write Reset 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 WD...

Страница 541: ...h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_TMROUTH field descriptions Field Description 15 0 TIMEROUTHIGH Shows the value of the upp...

Страница 542: ...16h offset 4005_2016h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 PRESCVAL 0 Write Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field Description 15 11 Reserved This read o...

Страница 543: ...gh byte of the refresh unlock register contains any value other than high bytes of the two values making up the sequence it is treated as an exception condition leading to a reset or interrupt then re...

Страница 544: ...Delay The watchdog uses glitch free multiplexers at two places one to choose between the LPO oscillator input and alternate clock input and the other to choose between the watchdog functional clock an...

Страница 545: ...ry steps of unlocking and configuring the watchdog The watchdog continues to be in its functional test mode and therefore you should pull the watchdog out of the functional test mode within WCT time o...

Страница 546: ...Restrictions on Watchdog Operation K53 Sub Family Reference Manual Rev 6 Nov 2011 546 Freescale Semiconductor Inc...

Страница 547: ...nal or external reference clocks as a source for the MCU system clock The MCG operates in conjuction with a crystal oscillator which allows an external crystal ceramic resonator or another external cl...

Страница 548: ...or the fast clock can be selected as the clock source for the MCU Can be used as a clock source for other on chip peripherals Control signals for the MCG external reference low power oscillator clock...

Страница 549: ...ovided as a clock source for other on chip peripherals MCG FLL Clock MCGFLLCLK is provided as a clock source for other on chip peripherals MCG Fixed Frequency Clock MCGFFCLK is provided as a clock sou...

Страница 550: ...ock Clock Generator PRDIV LOLIE Sync Auto Trim Machine IRCST PLLST CLKST ATMS SCTRIM SCFTRIM FCTRIM ATMST IREFSTEN OSCINIT EREFS HGO RANGE External DRS 2 Clock Valid Peripheral BUSCLK PLLCLKEN MCGPLLC...

Страница 551: ...ion page 4006_4000 MCG Control 1 Register MCG_C1 8 R W 04h 24 3 1 552 4006_4001 MCG Control 2 Register MCG_C2 8 R W See section 24 3 2 553 4006_4002 MCG Control 3 Register MCG_C3 8 R W Undefined 24 3...

Страница 552: ...RANGE 0 Divide Factor is 2 for all other RANGE values Divide Factor is 64 010 If RANGE 0 Divide Factor is 4 for all other RANGE values Divide Factor is 128 011 If RANGE 0 Divide Factor is 8 for all ot...

Страница 553: ...ted for the crystal oscillator 01 Encoding 1 High frequency range selected for the crystal oscillator 1X Encoding 2 Very high frequency range selected for the crystal oscillator 3 HGO High Gain Oscill...

Страница 554: ...Clock Trim Setting SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period The SCTRIM bits are binary weighted that is bit 1 adjusts twice...

Страница 555: ...ange 00 0 31 25 39 0625 kHz 640 20 25 MHz 1 32 768 kHz 732 24 MHz 01 0 31 25 39 0625 kHz 1280 40 50 MHz 1 32 768 kHz 1464 48 MHz 10 0 31 25 39 0625 kHz 1920 60 75 MHz 1 32 768 kHz 2197 72 MHz 11 0 31...

Страница 556: ...hat value from the nonvolatile memory location to this bit 1 A value for FCTRIM is loaded during reset from a factory programmed location 2 A value for SCFTRIM is loaded during reset from a factory pr...

Страница 557: ...e PLL The resulting frequency must be in the range of 2 MHz to 4 MHz After the PLL is enabled by setting either PLLCLKEN or PLLS the PRDIV value must not be changed when LOCK is zero Table 24 7 PLL Ex...

Страница 558: ...external clock indication The CME bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock FEE FBE PEE PBE or BLPE Whenever the CME bit is set to a logi...

Страница 559: ...s for the PLL LOLS is set if after acquiring lock the PLL output frequency has fallen outside the lock exit frequency tolerance D unl LOLIE determines whether an interrupt request is made when LOLS is...

Страница 560: ...FLL reference clock is the external reference clock 1 Source of FLL reference clock is the internal reference clock 3 2 CLKST Clock Mode Status These bits indicate the current clock mode The CLKST bit...

Страница 561: ...Machine Select Selects the IRCS clock for Auto Trim Test 0 32 kHz Internal Reference Clock selected 1 4 MHz Internal Reference Clock selected 5 ATMF Automatic Trim machine Fail Flag Fail flag for the...

Страница 562: ...ATCVL Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVL field descriptions Field Description 7 0 ATCVL ATM Compare Value Low Values are used by Auto Trim Machine to compare and adjust Internal Reference trim valu...

Страница 563: ...k mode and the C1 CLKS and S CLKST will automatically be set to 2 b10 If entering Normal Stop mode when the MCG is in PEE mode with C5 PLLSTEN 0 the MCG will reset to PBE clock mode and C1 CLKS and S...

Страница 564: ...ency to the FLL factor as selected by C4 DRST_DRS and C4 DMX32 bits times the external reference frequency as specified by the C1 FRDIV and C2 RANGE Refer to the C4 DMX32 bit description for more deta...

Страница 565: ...C6 PLLS bit is written to 1 In PEE mode the MCGOUTCLK is derived from the PLL clock which is controlled by the external reference clock The PLL clock frequency locks to a multiplication factor as spec...

Страница 566: ...ed and all MCG clock signals are static except in the following case MCGPLLCLK is active in Normal Stop mode when PLLSTEN 1 MCGIRCLK is active in Stop mode when all the following conditions become tru...

Страница 567: ...s shown by the C4 DRST_DRS read bits 24 4 2 Low Power Bit Usage The C2 LP bit is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used The C4 DR...

Страница 568: ...n C6 CME 1 a loss of clock is detected if the OSC external reference falls below a minimum frequency floc_high or floc_low depending on C2 RANGE Upon detect of a loss of clock event the MCU generates...

Страница 569: ...or ATC or if Stop mode is entered If an abort occurs ATC ATMF fail flag is asserted The ATM machine uses the bus clock as the external reference clock to perform the IRC auto trim Therefore it is req...

Страница 570: ...the MCG and properly switch between the various available modes 24 5 1 MCG Module Initialization Sequence The MCG comes out of reset configured for FEI mode The internal reference will stabilize in ti...

Страница 571: ...tely reflecting that the MCG has moved into the proper mode If the MCG is in FEE FBE PEE PBE or BLPE mode and C2 EREFS was also set in step 1 wait here for S OSCINIT bit to become set indicating that...

Страница 572: ...ce if the maximum high range DCO frequency that can be achieved with a 32 768 kHz reference is desired set C4 DRST_DRS bits to 2 b11 and set C4 DMX32 bit to 1 The resulting DCO output MCGOUTCLK freque...

Страница 573: ...must be set to 2 b00 and the C1 FRDIV bits must be set to 3 b000 to ensure this clock is divided by 1 to keep it within the allowed FLL reference clock range 24 5 3 MCG Mode Switching When switching b...

Страница 574: ...s and M is the multiplier selected by C6 VDIV bits This section will include 3 mode switching examples using an 4 MHz external crystal If using an external clock source less than 2 MHz the MCG should...

Страница 575: ...transition either directly to PBE mode or first through BLPE mode and then to PBE mode a BLPE If a transition through BLPE mode is desired first set C2 LP to 1 b BLPE PBE C6 0x40 C6 PLLS set to 1 sele...

Страница 576: ...the output of the PLL as the system clock source b Loop until S CLKST are 2 b11 indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode Now With PRDIV of divide by 2 and...

Страница 577: ...MODE C2 0x1E C2 LP 1 CHECK CHECK C1 0x10 CHECK CONTINUE IN PEE MODE S PLLST 1 S LOCK 1 S CLKST 10 S CLKST 11 S LP 1 S IREFST 0 S OSCINIT 1 C5 0x01 C5 VDIV 1 Figure 24 13 Flowchart of FEI to PEE Mode T...

Страница 578: ...de a BLPE If a transition through BLPE mode is desired first set C2 LP to 1 b BLPE FBE C6 0x00 C6 PLLS clear to 0 to select the FLL At this time with C1 FRDIV value of 3 b010 the FLL divider is set to...

Страница 579: ...he internal reference clock has been selected as the reference clock source c Loop until S CLKST are 2 b01 indicating that the internal reference clock is selected to feed MCGOUTCLK 4 Lastly FBI trans...

Страница 580: ...IREFST 0 CHECK S CLKST 01 YES NO YES C2 LP 1 C6 0x00 IN BLPE MODE IN BLPE MODE NO YES C2 0x1C C2 LP 0 C2 0x1E ENTER BLPE MODE C2 LP 1 Figure 24 14 Flowchart of PEE to BLPI Mode Transition using an 4 M...

Страница 581: ...to 2 b00 in order to select the output of the FLL as system clock source C1 FRDIV remain at 3 b010 or divide by 128 for a reference of 4 MHz 128 31 25 kHz C1 IREFS cleared to 0 selecting the external...

Страница 582: ...ill switch back to 640 C1 0x10 C2 0x00 C2 0x1C CHECK CHECK CHECK S OSCINIT 1 CONTINUE IN FEE MODE NO NO NO YES YES YES START IN BLPI MODE S IREFST 0 S CLKST 00 Figure 24 15 Flowchart of BLPI to FEE Mo...

Страница 583: ...MHz crystals and resonators High Range mode Automatic Gain Control AGC to optimize power consumption in high frequency ranges 3 8 MHz 8 32 MHz using low power mode High gain option in frequency range...

Страница 584: ...reference clock source in this MCU The following figure shows the block diagram of the OSC module XTAL EXTAL XTL_CLK CNT_DONE_4096 OSC_CLK_OUT Mux 4096 Counter OSC Clock Enable STOP OSC clock selectio...

Страница 585: ...ternal Caystal Resonator Connections Oscillator Mode Connections Low frequency 32 kHz low power Connection 1 Low frequency 32 kHz high gain Connection 2 Connection 31 High frequency 3 32 MHz low power...

Страница 586: ...the CR SCxP bits OSC VSS Cx Cy RF Crystal or Resonator XTAL EXTAL Figure 25 4 Crystal Ceramic Resonator Connections Connection 3 25 6 External Clock Connections In external clock mode the pins can be...

Страница 587: ...25 71 1 587 25 71 1 OSC Control Register OSC_CR After OSC is enabled and starts generating the clocks the configurations such as low power and frequency range must not be changed Address OSC_CR is 400...

Страница 588: ...P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load 0 Disable the selection 1 Add 2 pF capacitor to the oscillator load 2 SC4P Oscillator 4 pF Capacitor Load Configure Configures...

Страница 589: ...Module State Diagram NOTE XTL_CLK is the clock generated internally from OSC circuits 25 8 1 1 Off The OSC enters the Off state when the system does not require OSC clocks Upon entering this state XT...

Страница 590: ...high In this state the OSC module is producing a stable output clock on OSC_CLK_OUT Its frequency is determined by the external components being used 25 8 1 4 External Clock Mode The OSC enters extern...

Страница 591: ...t to logic levels In this mode the internal capacitors could be used 25 8 2 2 Low Frequency Low Power Mode In low frequency low power mode the oscillator uses a gain control loop to minimize power con...

Страница 592: ...ential It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels 25 8 3 Counter The oscillator output clock OSC_CLK_OUT is gated off...

Страница 593: ...ter settings If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes the OSC is still functional in these modes After waking up from Very Low Leakage Stop VLLSx modes all OSC regis...

Страница 594: ...Interrupts K53 Sub Family Reference Manual Rev 6 Nov 2011 594 Freescale Semiconductor Inc...

Страница 595: ...1 Features and Modes The key features of the RTC oscillator are as follows Supports 32 kHz crystals with very low power Consists of internal feed back resistor Consists of internal programmable capac...

Страница 596: ...n to find out which signals are actually connected to the external pins Table 26 1 RTC Signal Descriptions Signal Description I O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O 26 2 1 EXTAL32 O...

Страница 597: ...lies the negative resistor for the RTC oscillator The gain of the amplifier is controlled by the amplitude detector which optimizes the power consumption A schmitt trigger is used to translate the sin...

Страница 598: ...There is no reset state associated with the RTC oscillator 26 7 Interrupts The RTC oscillator does not generate any interrupts Reset Overview K53 Sub Family Reference Manual Rev 6 Nov 2011 598 Freesca...

Страница 599: ...e memory and uses this information to ensure a proper interface The following table shows the supported 8 bit 16 bit and 32 bit read write operations Flash memory type Read Write Program flash memory...

Страница 600: ...ogram flash memory and FlexMemory to the device 64 bit prefetch speculation buffer with controls for instruction data access per master and bank 4 way 8 set 64 bit line size cache for a total of thirt...

Страница 601: ...Supervisor privileged mode only 32 bits NOTE Accesses to unimplemented registers within the FMC s 4 KB address space return a bus error The cache entries both data and tag valid can be read at any tim...

Страница 602: ...ol Register FMC_PFB1CR 32 R W 3002_001Fh 27 4 3 613 4001_F100 Cache Tag Storage FMC_TAGVDW0S0 32 R W 0000_0000h 27 4 4 615 4001_F104 Cache Tag Storage FMC_TAGVDW0S1 32 R W 0000_0000h 27 4 4 615 4001_F...

Страница 603: ...6 617 4001_F154 Cache Tag Storage FMC_TAGVDW2S5 32 R W 0000_0000h 27 4 6 617 4001_F158 Cache Tag Storage FMC_TAGVDW2S6 32 R W 0000_0000h 27 4 6 617 4001_F15C Cache Tag Storage FMC_TAGVDW2S7 32 R W 00...

Страница 604: ...224 Cache Data Storage lower word FMC_DATAW0S4L 32 R W 0000_0000h 27 4 9 620 4001_F228 Cache Data Storage upper word FMC_DATAW0S5U 32 R W 0000_0000h 27 4 8 619 4001_F22C Cache Data Storage lower word...

Страница 605: ...274 Cache Data Storage lower word FMC_DATAW1S6L 32 R W 0000_0000h 27 4 11 622 4001_F278 Cache Data Storage upper word FMC_DATAW1S7U 32 R W 0000_0000h 27 4 10 621 4001_F27C Cache Data Storage lower wor...

Страница 606: ...F2C4 Cache Data Storage lower word FMC_DATAW3S0L 32 R W 0000_0000h 27 4 15 626 4001_F2C8 Cache Data Storage upper word FMC_DATAW3S1U 32 R W 0000_0000h 27 4 14 625 4001_F2CC Cache Data Storage lower wo...

Страница 607: ...6 5 4 3 2 1 0 R M7AP 1 0 M6AP 1 0 M5AP 1 0 M4AP 1 0 M3AP 1 0 M2AP 1 0 M1AP 1 0 M0AP 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FMC_PFAPR field descriptions Field Description 31 24 Reserved This read...

Страница 608: ...rol whether prefetching is enabled based on the logical number of the requesting crossbar switch master This field is further qualified by the PFBnCR BxDPE BxIPE bits 0 Prefetching for this master is...

Страница 609: ...owed based on the logical master number of the requesting crossbar switch master 00 No access may be performed by this master 01 Only read accesses may be performed by this master 10 Only write access...

Страница 610: ...0 Control Register FMC_PFB0CR Address FMC_PFB0CR is 4001_F000h base 4h offset 4001_F004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R B0RWSC 3 0 CLCK_WAY 3 0 0 0 B0MW 1 0 0 W CINV_WAY 3 0 S_B...

Страница 611: ...corresponding cache 1 Invalidate cache way for the corresponding cache clear the tag data and vld bits of ways selected 19 S_B_INV Invalidate Prefetch Speculation Buffer This bit determines if the FM...

Страница 612: ...ences 1 Enable prefetches in response to data references 1 B0IPE Bank 0 Instruction Prefetch Enable This bit controls whether prefetches or speculative accesses are initiated in response to instructio...

Страница 613: ...he read access time of the flash array expressed in system clock cycles and RWSC is defined as Access time of flash array system clocks RWSC 1 The FMC automatically calculates this value based on the...

Страница 614: ...erences 1 Enable prefetches in response to data references 1 B1IPE Bank 1 Instruction Prefetch Enable This bit controls whether prefetches or speculative accesses are initiated in response to instruct...

Страница 615: ...t 4001_F110h FMC_TAGVDW0S5 is 4001_F000h base 114h offset 4001_F114h FMC_TAGVDW0S6 is 4001_F000h base 118h offset 4001_F118h FMC_TAGVDW0S7 is 4001_F000h base 11Ch offset 4001_F11Ch Bit 31 30 29 28 27...

Страница 616: ...et 4001_F130h FMC_TAGVDW1S5 is 4001_F000h base 134h offset 4001_F134h FMC_TAGVDW1S6 is 4001_F000h base 138h offset 4001_F138h FMC_TAGVDW1S7 is 4001_F000h base 13Ch offset 4001_F13Ch Bit 31 30 29 28 27...

Страница 617: ...t 4001_F150h FMC_TAGVDW2S5 is 4001_F000h base 154h offset 4001_F154h FMC_TAGVDW2S6 is 4001_F000h base 158h offset 4001_F158h FMC_TAGVDW2S7 is 4001_F000h base 15Ch offset 4001_F15Ch Bit 31 30 29 28 27...

Страница 618: ...et 4001_F170h FMC_TAGVDW3S5 is 4001_F000h base 174h offset 4001_F174h FMC_TAGVDW3S6 is 4001_F000h base 178h offset 4001_F178h FMC_TAGVDW3S7 is 4001_F000h base 17Ch offset 4001_F17Ch Bit 31 30 29 28 27...

Страница 619: ...TAW0S2U is 4001_F000h base 210h offset 4001_F210h FMC_DATAW0S3U is 4001_F000h base 218h offset 4001_F218h FMC_DATAW0S4U is 4001_F000h base 220h offset 4001_F220h FMC_DATAW0S5U is 4001_F000h base 228h...

Страница 620: ...DATAW0S2L is 4001_F000h base 214h offset 4001_F214h FMC_DATAW0S3L is 4001_F000h base 21Ch offset 4001_F21Ch FMC_DATAW0S4L is 4001_F000h base 224h offset 4001_F224h FMC_DATAW0S5L is 4001_F000h base 22C...

Страница 621: ...TAW1S2U is 4001_F000h base 250h offset 4001_F250h FMC_DATAW1S3U is 4001_F000h base 258h offset 4001_F258h FMC_DATAW1S4U is 4001_F000h base 260h offset 4001_F260h FMC_DATAW1S5U is 4001_F000h base 268h...

Страница 622: ...DATAW1S2L is 4001_F000h base 254h offset 4001_F254h FMC_DATAW1S3L is 4001_F000h base 25Ch offset 4001_F25Ch FMC_DATAW1S4L is 4001_F000h base 264h offset 4001_F264h FMC_DATAW1S5L is 4001_F000h base 26C...

Страница 623: ...TAW2S2U is 4001_F000h base 290h offset 4001_F290h FMC_DATAW2S3U is 4001_F000h base 298h offset 4001_F298h FMC_DATAW2S4U is 4001_F000h base 2A0h offset 4001_F2A0h FMC_DATAW2S5U is 4001_F000h base 2A8h...

Страница 624: ...DATAW2S2L is 4001_F000h base 294h offset 4001_F294h FMC_DATAW2S3L is 4001_F000h base 29Ch offset 4001_F29Ch FMC_DATAW2S4L is 4001_F000h base 2A4h offset 4001_F2A4h FMC_DATAW2S5L is 4001_F000h base 2AC...

Страница 625: ...TAW3S2U is 4001_F000h base 2D0h offset 4001_F2D0h FMC_DATAW3S3U is 4001_F000h base 2D8h offset 4001_F2D8h FMC_DATAW3S4U is 4001_F000h base 2E0h offset 4001_F2E0h FMC_DATAW3S5U is 4001_F000h base 2E8h...

Страница 626: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data 31 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnL field descriptions Field De...

Страница 627: ...ally The register controls enable buffering and prefetching per memory bank and access type instruction fetch or data reference The cache also supports three types of LRU replacement algorithms LRU pe...

Страница 628: ...Functional description K53 Sub Family Reference Manual Rev 6 Nov 2011 628 Freescale Semiconductor Inc...

Страница 629: ...g operations without the need for any external high voltage power sources The FTFL module includes a memory controller that executes commands to modify flash memory contents An erased bit reads 1 and...

Страница 630: ...rogram or erase of stored data Automated built in program and erase algorithms with verify Section programming for faster bulk programming times For devices containing only program flash memory Read a...

Страница 631: ...ase of data written for EEPROM Built in hardware emulation scheme to automate EEPROM record maintenance functions Programmable EEPROM data set size and FlexNVM partition code facilitating EEPROM memor...

Страница 632: ...TFL module is shown in the following figure For devices with FlexNVM feature FlexNVM FlexRAM Program flash EEPROM backup To MCU s flash controller Interrupt Control registers Status registers Register...

Страница 633: ...for user data boot code and additional code store Data flash sector The data flash sector is the smallest portion of the data flash memory that can be erased EEPROM Using a built in filing system the...

Страница 634: ...thin the FTFL module which provides the nonvolatile memory storage FlexMemory FTFL configuration that supports data flash EEPROM and FlexRAM FlexNVM Block The FlexNVM block can be configured to be use...

Страница 635: ...ata retention limit may be reached from the last erase operation not from the programming time RWW Read While Write The ability to simultaneously read from one memory resource while commanded operatio...

Страница 636: ...flash only devices Reserved FlexNVM devices EEPROM protection byte Refer to the description of the EEPROM Protection Register FEPROT 0x0_040D 1 Flash nonvolatile option byte Refer to the description o...

Страница 637: ...ogram capabilities in the data flash IFR see the Program Partition command in Program Partition Command the Erase All Blocks command in Erase All Blocks Command and the Read Resource command in Read R...

Страница 638: ...RAM for EEPROM use NOTE EEESIZE must be 0 bytes 1111b when the FlexNVM partition code FlexNVM Partition Code is set to No EEPROM 0000 Reserved 0001 Reserved 0010 4 096 Bytes 0011 2 048 Bytes 0100 1 02...

Страница 639: ...sh KByte EEPROM backup KByte 0000 256 0 0001 Reserved Reserved 0010 Reserved Reserved 0011 224 32 0100 192 64 0101 128 128 0110 0 256 0111 Reserved Reserved 1000 0 256 1001 Reserved Reserved 1010 Rese...

Страница 640: ...28 34 5 647 4002_0006 Flash Common Command Object Registers FTFL_FCCOB1 8 R W 00h 28 34 5 647 4002_0007 Flash Common Command Object Registers FTFL_FCCOB0 8 R W 00h 28 34 5 647 4002_0008 Flash Common C...

Страница 641: ...not writable NOTE When set the Access Error ACCERR and Flash Protection Violation FPVIOL bits in this register prevent the launch of any more commands or writes to the FlexRAM when EEERDY is set until...

Страница 642: ...rror detected 1 Access error detected 4 FPVIOL Flash Protection Violation Flag The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area of program flash or...

Страница 643: ...never an FTFL read collision error is detected see the description of FSTAT RDCOLERR 5 ERSAREQ Erase All Request This bit issues a request to the memory controller to execute the Erase All Blocks comm...

Страница 644: ...run to partition the FlexNVM block for EEPROM The RAMRDY flag sets after completion of the Erase All Blocks command or execution of the erase all operation triggered external to the FTFL For devices w...

Страница 645: ...eld is set to unsecure the MEEN setting does not matter 00 Mass erase is enabled 01 Mass erase is enabled 10 Mass erase is disabled 11 Mass erase is enabled 3 2 FSLACC Freescale Failure Analysis Acces...

Страница 646: ...te of these read only bits which are loaded from NVM at reset The function of the bits is defined in the device s Chip Configuration details All bits in the register are read only During the reset seq...

Страница 647: ...o command buffering or queueing is provided the next command can be loaded only after the current command completes Some commands return information to the FCCOB registers Any values returned to FCCOB...

Страница 648: ...tected regions can be changed by program and erase operations The four FPROT registers allow 32 protectable regions Each bit protects a 1 32 region of the program flash memory The bitfields are define...

Страница 649: ...ored In NVM Special mode All bits of FPROT are writable without restriction Unprotected areas can be protected and protected areas can be unprotected Restriction The user must never write to any FPROT...

Страница 650: ...ransitions are accepted while all bits with 0 to 1 transitions are ignored In NVM Special mode All bits of the FEPROT register are writable without restriction Unprotected areas can be protected and p...

Страница 651: ...This 1 to 0 transition check is performed on a bit by bit basis Those FDPROT bits with 1 to 0 transitions are accepted while all bits with 0 to 1 transitions are ignored In NVM Special mode All bits...

Страница 652: ...s within the memory map See Swap Control Command for details 28 4 2 Flash Protection Individual regions within the flash memory can be protected from program and erase operations Protection is control...

Страница 653: ...8 Data flash size 8 Data flash size 8 Data flash size 8 DPROT4 EEPROM backup EEPROM backup size DEPART Last FlexNVM address Figure 28 28 Data flash protection For the non 2n data flash sizes 192KB an...

Страница 654: ...sh protection 192 and 224KB FEPROT Protects eight regions of the EEPROM memory as shown in the following figure EEPROM size 8 EPROT0 0x0_0000 EPROT1 EPROT2 EPROT5 EPROT7 EPROT6 FlexRAM Last EEPROM add...

Страница 655: ...tire lifetime of a given application The FlexNVM partition code choices affect the endurance and data retention characteristics of the device 28 4 3 2 EEPROM User Perspective The EEPROM system is show...

Страница 656: ...partitioned EEPROM backup One subsystem A is 1 8 1 4 or 1 2 of the partitioned FlexRAM with the remainder belonging to the other subsystem B The partition information EEESIZE DEPART EEESPLIT is stored...

Страница 657: ...F and FCNFG EEERDY bits are set after data from all valid EEPROM data records is copied to the FlexRAM After the CCIF bit is set the FlexRAM is available for read or write access When configured for E...

Страница 658: ...different partitions of the FlexNVM are available the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given applic...

Страница 659: ...ts are shown in the following table Table 28 30 FTFL Interrupt Sources FTFL Event Readable Status Bit Interrupt Enable Bit FTFL Command Complete FSTAT CCIF FCNFG CCIE FTFL Read Collision Error FSTAT R...

Страница 660: ...wo operating modes NVM Normal and NVM Special The operating mode affects the command set availability see Table 28 31 Refer to the Chip Configuration details of this device for how to activate each mo...

Страница 661: ...ot possible The following simultaneous accesses are allowed for devices with program flash only The user may read from one logical program flash memory space while commands typically program and erase...

Страница 662: ...nd The individual registers that make up the FCCOB data set can be written in any order 28 4 10 1 2 Launch the Command by Clearing CCIF Once all relevant command parameters have been loaded the user l...

Страница 663: ...ting the FSTAT CCIF bit 2 If the parameter and protection checks pass the command proceeds to execution Run time errors such as failure to erase verify may occur during the execution phase Run time er...

Страница 664: ...STAT register Write 0x30 to FSTAT register no yes no yes Previous command complete no CCIF 1 yes START Figure 28 34 Generic FTFL Command Write Sequence Flowchart 28 4 10 2 FTFL Commands The following...

Страница 665: ...ogrammed locations at margin read levels 0x03 Read Resource IFR ID IFR IFR Read 4 bytes from program flash IFR data flash IFR or version ID 0x06 Program Longword Program 4 bytes in a program flash blo...

Страница 666: ...s Verify that all program flash data flash blocks EEPROM backup data records and data flash IFR are erased then release MCU security 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the...

Страница 667: ...all memory locations are unprotected 0x45 Verify Backdoor Access Key Release MCU security after comparing a set of user supplied security keys to those stored in the program flash 0x46 Swap Control Ha...

Страница 668: ...FTFL commands that can be executed in each flash operating mode Table 28 31 FTFL Commands by Mode FCMD Command NVM Normal NVM Special Unsecure Secure MEEN 10 Unsecure Secure MEEN 10 0x00 Read 1s Block...

Страница 669: ...e FlexNVM FlexRAM functionality For devices containing FlexNVM Table 28 32 Allowed Simultaneous Memory Operations Program Flash Data Flash FlexRAM Read Program Sector Erase Read Program Sector Erase R...

Страница 670: ...d be employed only in special cases They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end of life data loss customary of flash memory dev...

Страница 671: ...occur There is an unrecognized command code in the FCCOB FCMD field There is an error in a FCCOB field for the specific commands Refer to the error handling table provided for each command Ensure that...

Страница 672: ...Block command aborts setting the FSTAT ACCERR bit If the FTFL fails to read all 1s i e the flash block is not fully erased the FSTAT MGSTAT0 bit is set The CCIF flag sets after the Read 1s Block opera...

Страница 673: ...s all locations within the specified section of flash memory If the FTFL fails to read all 1s i e the flash section is not erased the FSTAT MGSTAT0 bit is set The CCIF flag sets after the Read 1s Sect...

Страница 674: ...If the comparison at margin 1 fails the MGSTAT0 bit is set The FTFL then sets the read margin for 0s re reads and compares again If the comparison at margin 0 fails the MGSTAT0 bit is set The CCIF fla...

Страница 675: ...source is assigned a select code as shown in Table 28 44 Table 28 43 Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents 7 0 0 0x03 RDRSRC 1 Flash address 23 16 2 Flash address 15 8 3...

Страница 676: ...12 5 Program Longword Command The Program Longword command programs four previously erased bytes in the program flash memory or in the data flash memory using an embedded algorithm CAUTION A Flash mem...

Страница 677: ...yte 2 data is programmed to byte address start 0b10 and Byte 3 data is programmed to byte address start 0b11 Table 28 47 Program Longword Command Error Handling Error Condition Error Bit Command not a...

Страница 678: ...nge FSTAT ACCERR Data flash is selected with EEPROM enabled FSTAT ACCERR Flash address is not longword aligned FSTAT ACCERR Any area of the selected flash block is protected FSTAT FPVIOL Any errors ha...

Страница 679: ...rites to FTFL registers are ignored except for writes to the FSTAT and FCNFG registers If an Erase Flash Sector operation effectively completes before the FTFL detects that a suspend request has been...

Страница 680: ...operation is aborted the FTFL starts the new command using the new FCCOB contents While FCNFG ERSSUSP is set a write to the FlexRAM while FCNFG EEERDY is set clears ERSSUSP and aborts the suspended op...

Страница 681: ...xecute Yes DONE No ERSSUSP 1 Save Erase Algo Set CCIF No Yes Start New Resume Erase No Abort User Cmd Interrupt Suspend Set SUSPACK 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Complete...

Страница 682: ...3 Flash address 7 0 1 4 Number of phrases to program 15 8 5 Number of phrases to program 7 0 1 Must be phrase aligned Flash address 2 0 000 After clearing CCIF to launch the Program Section command th...

Страница 683: ...g The process of programming an entire flash sector using the Program Section command is as follows 1 If required execute the Set FlexRAM Function command to make the FlexRAM available as traditional...

Страница 684: ...eleased by setting the FSEC SEC field to the unsecure state The security byte in the flash configuration field see Flash Configuration Field Description remains unaffected by the Read 1s All Blocks co...

Страница 685: ...Once byte 1 value 6 Read Once byte 2 value 7 Read Once byte 3 value After clearing CCIF to launch the Read Once command a 4 byte Read Once record is read from the program flash IFR and stored in the F...

Страница 686: ...ided The Program Once command also verifies that the programmed values read back correctly The CCIF flag is set after the Program Once operation has completed The reserved program flash 0 IFR location...

Страница 687: ...FSTAT MGSTAT0 bit is set The CCIF flag is set after the Erase All Blocks operation completes Table 28 62 Erase All Blocks Command Error Handling Error Condition Error Bit Command not available in cur...

Страница 688: ...in the Flash Configuration Field Table 28 63 Verify Backdoor Access Key Command FCCOB Requirements FCCOB Number FCCOB Contents 7 0 Flash Configuration Field Offset Address 0 0x45 VFYKEY 1 3 Not Used...

Страница 689: ...ontrol Command The Swap Control command handles specific activities associated with swapping the two logical program flash memory blocks within the memory map Table 28 65 Swap Control Command FCCOB Re...

Страница 690: ...currently active program flash block will be programmed to 0xFF00 0x04 Progress Swap to COMPLETE State After verifying that the current swap state is UPDATE ERASED and that the flash address provided...

Страница 691: ...d Erase Flash Sector command operations unless the swap indicator being erased is in the non active program flash block and the swap system is in the UPDATE or UPDATE ERASED state Once the swap system...

Страница 692: ...e swap determination and program verify operations 1 2 4 FSTAT MGSTAT0 Any brownouts were detected during the swap determination procedure 8 FSTAT MGSTAT0 1 Returned fields will not be updated i e no...

Страница 693: ...0xFF00 0xFFFF 0x0000 Swap State Indicator0 Indicator1 Legend Swap Control Code 4 UpErs0 0xFF00 0xFFFF 2 Update1 0x0000 0xFF00 Erase ERSBLK or ERSSCR commands Reset POR VLLSx exit warm system reset Un...

Страница 694: ...date 2 1 0 20 0x0000 0xFF 00 0xFFXX Update 2 1 0 216 0x0000 0x0000 0x0000 Update 2 1 0 226 0x0000 0xXXXX 0xXXXX Update 2 1 0 23 0x0000 0xFFFF7 0xFF00 Update 2 1 1 24 0x0000 0xXXXX 0xFF00 Update 2 1 1...

Страница 695: ...itializes the FlexRAM The Program Partition command must not be launched from flash memory since flash memory resources are not accessible during Program Partition command execution CAUTION While diff...

Страница 696: ...64 192 10 0x6 128 128 11 0x6 128 128 00 0x5 64 448 01 0x5 128 384 10 0x5 256 256 11 0x5 256 256 00 0x4 128 896 01 0x4 256 768 10 0x4 512 512 11 0x4 512 512 00 0x3 256 1 792 01 0x3 512 1 536 10 0x3 1...

Страница 697: ...ectors are formatted for EEPROM use The CCIF flag is set after the Program Partition operation completes Prior to launching the Program Partition command the data flash IFR must be in an erased state...

Страница 698: ...Function Control FlexRAM Function Control Code Action 0xFF Make FlexRAM available as RAM Clear the FCNFG EEERDY and FCNFG RAMRDY flags Write a background of ones to all FlexRAM locations Set the FCNF...

Страница 699: ...xRAM Function Command Error Handling Error Condition Error Bit Command not available in current mode security FSTAT ACCERR FlexRAM Function Control Code is not defined FSTAT ACCERR FlexRAM Function Co...

Страница 700: ...dge of the contents of the 8 byte backdoor key value stored in the Flash Configuration Field see Flash Configuration Field Description If the FSEC KEYEN bits are in the enabled state the Verify Backdo...

Страница 701: ...ram and erase protections defined in the program flash protection registers If the backdoor keys successfully match the unsecured chip has full control of the contents of the Flash Configuration Field...

Страница 702: ...Flash Operation in Low Power Modes K53 Sub Family Reference Manual Rev 6 Nov 2011 702 Freescale Semiconductor Inc...

Страница 703: ...bus interface called the FlexBus interface controller is provided on the device with basic functionality of interfacing to slave only devices It can be directly connected to the following asynchronou...

Страница 704: ...le option helps with glueless connections to synchronous and asynchronous memory devices 29 1 3 Modes of Operation The external interface is a configurable multiplexed bus set to one of the following...

Страница 705: ...1 0 Transfer size O FB_TBST Burst transfer indicator O FB_TA Transfer acknowledge I FB_CLK FlexBus clock output O 29 2 1 Address and Data Buses FB_An FB_Dn FB_ADn In non multiplexed mode the FB_A 31 0...

Страница 706: ...interfacing memory and or peripheral to enable a read transfer FB_OE is only asserted during read accesses when a chip select matches the current address decode 29 2 5 Read Write FB_R W The processor...

Страница 707: ...and then shows the port size Table 29 2 Data Transfer Size FB_TSIZ 1 0 Transfer Size 00 4 bytes 01 1 byte 10 2 bytes 11 16 bytes line For burst inhibited transfers FB_TSIZ 1 0 changes with each FB_TS...

Страница 708: ...t continue to drive data until FB_TA is recognized For write cycles the processor continues driving data one clock after FB_CSn is negated The number of wait states is determined by CSCRn or the exter...

Страница 709: ...select address register FB_CSAR2 32 R W 0000_0000h 29 3 1 710 4000_C01C Chip select mask register FB_CSMR2 32 R W 0000_0000h 29 3 2 711 4000_C020 Chip select control register FB_CSCR2 32 R W 0000_0000...

Страница 710: ...egisters appropriately Addresses FB_CSAR0 is 4000_C000h base 0h offset 4000_C000h FB_CSAR1 is 4000_C000h base Ch offset 4000_C00Ch FB_CSAR2 is 4000_C000h base 18h offset 4000_C018h FB_CSAR3 is 4000_C0...

Страница 711: ...and CSMR0 BAM equals 0x0008 FB_CS0 addresses two discontinuous 64 KB memory blocks one from 0x40_0000 0x40_FFFF and one from 0x48_0000 0x48_FFFF Likewise for FB_CS0 to access 32 MB of address space st...

Страница 712: ...for your particular device for information on the exact CSCR0 reset value Addresses FB_CSCR0 is 4000_C000h base 8h offset 4000_C008h FB_CSCR1 is 4000_C000h base 14h offset 4000_C014h FB_CSCR2 is 4000_...

Страница 713: ...the termination during a read cycle that hits in the chip select address space NOTE The hold time applies only at the end of a transfer Therefore during a burst transfer or a transfer to a port size...

Страница 714: ...ociated with each chip select It determines where data is driven during write cycles and where data is sampled during read cycles 00 32 bit port size Valid data sampled and driven on FB_D 31 0 01 8 bi...

Страница 715: ...a reserved value writing to a reserved bit location in this register or not accessing this register as 32 bit Address FB_CSPMCR is 4000_C000h base 60h offset 4000_C060h Bit 31 30 29 28 27 26 25 24 23...

Страница 716: ...he FB_TA FB_CS3 and FB_BE_7_0 signals NOTE When GROUP5 is not 0000 you must set the CSCRn AA bit Else the bus hangs during a transfer 0000 FB_TA 0001 FB_CS3 You must also set CSCRn AA 0010 FB_BE_7_0 Y...

Страница 717: ...ol register If CSMR WP is set and a write access is performed the internal bus cycle terminates with a bus error no chip select is asserted and no external bus cycle is performed No The access is term...

Страница 718: ...32 bit data ports Transfer parameters address setup and hold port size the number of wait states for the external device being accessed automatic internal transfer termination enable or disable and bu...

Страница 719: ...ess values Driven with address values FB_D 31 24 FB_D 23 16 FB_D 15 8 FB_D 7 0 FB_BE_7_0 FB_BE_15_8 FB_BE_23_16 FB_BE_31_24 Byte 1 Byte 0 Byte 3 Byte 2 Byte 0 Byte 1 Byte 2 Byte 3 Figure 29 24 Connect...

Страница 720: ...bus operations occur in four clocks 1 S0 At the first clock edge the address attributes and FB_TS FB_ALE are driven 2 S1 FB_CSn is asserted at the second rising clock edge to indicate the device selec...

Страница 721: ...X for writes and FB_AD 31 X is tristated for reads Address continues to be driven on the FB_AD pins that are unused for data If FB_TA is recognized asserted then the cycle moves on to S2 If FB_TA is n...

Страница 722: ...cycle flowchart 1 Decode address 3 Assert FB_TA external termination 1 Negate FB_TA external termination 1 Set FB_R W to read 2 Assert FB_CSn auto acknowledge internal termination 2 Sample FB_TA low a...

Страница 723: ...d data busses are muxed between the FlexBus and another module At the end of the read bus cycles the address signals are indeterminate Address Address Data TSIZ AA 1 AA 0 AA 1 AA 0 FB_CLK FB_A Y FB_D...

Страница 724: ...appropriate slave device 1 Negate transfer start 2 Assert FB_CSn 3 Drive data 1 FlexBus asserts internal FB_TA auto acknowledge internal termination FlexBus Figure 29 28 Write Cycle Flowchart The foll...

Страница 725: ...llustrates the basic byte read transfer to an 8 bit device with no wait states The address is driven on the full FB_AD 31 8 bus in the first clock The device tristates FB_AD 31 24 on the second clock...

Страница 726: ...n FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 30 Single Byte Read Transfer The following figure shows the similar configuration for a write transfer The data is driven from the second clock on FB_AD 31 24...

Страница 727: ...a 16 bit device with no wait states The address is driven on the full FB_AD 31 8 bus in the first clock The device tristates FB_AD 31 16 on the second clock and continues to drive address on FB_AD 15...

Страница 728: ...n FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 32 Single Word Read Transfer The following figure shows the similar configuration for a write transfer The data is driven from the second clock on FB_AD 31 16...

Страница 729: ...TA FB_TSIZ 1 0 Figure 29 33 Single Word Write Transfer 29 4 6 3 3 Bus Cycle Sizing Longword Transfer 32 bit Device No Wait States The following figure depicts a longword read from a 32 bit device Chap...

Страница 730: ...FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 34 Longword Read Transfer The following figure illustrates the longword write to a 32 bit device Functional Description K53 Sub...

Страница 731: ...address hold and time for a device to provide or latch data 29 4 6 4 1 Wait States Wait states can be inserted before each beat of a transfer by programming the CSCRn registers Wait states can give th...

Страница 732: ...AA 0 FB_CLK FB_A Y FB_D X FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 36 Basic Read Bus Cycle No Wait States Functional Description K53 Sub Family Reference Manual Rev 6 N...

Страница 733: ...states are used the S1 state repeats continuously until the the chip select auto acknowledge unit asserts internal transfer acknowledge or the external FB_TA is recognized as asserted The following fi...

Страница 734: ...A 1 AA 0 FB_CLK FB_A Y FB_D X FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 38 Read Bus Cycle One Wait State Functional Description K53 Sub Family Reference Manual Rev 6 Nov...

Страница 735: ...on of the chip selects byte selects and output enable can be programmed on a chip select basis Each chip select can be programmed to assert one to four clocks after transfer start address latch enable...

Страница 736: ...K FB_A Y FB_D X FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 40 Read Bus Cycle with Two Clock Address Setup No Wait States Functional Description K53 Sub Family Reference Ma...

Страница 737: ...on to address setup a programmable address hold option for each chip select exists Address and attributes can be held one to four clocks after chip select byte selects and output enable negate The fol...

Страница 738: ...CLK FB_A Y FB_D X FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 42 Read Cycle with Two Clock Address Hold No Wait States Functional Description K53 Sub Family Reference Manua...

Страница 739: ...BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 43 Write Cycle with Two Clock Address Hold No Wait States The following figure shows a bus cycle using address setup wait states and address hold Chapter 29 Externa...

Страница 740: ...indicates the size of the entire transfer For example with bursting enabled a 16 bit transfer to an 8 bit port takes two beats two byte sized transfers for which FB_TSIZ 1 0 equals 10b throughout A 32...

Страница 741: ...paces can be declared burst inhibited for reads and writes by clearing the appropriate CSCRn BSTR BSTW bits The following figure shows a 32 bit read to an 8 bit device programmed for burst enable The...

Страница 742: ...device with burst enabled The transfer results in a 4 beat burst and the data is driven on FB_AD 31 24 The transfer size is driven at 32 bit 00 throughout the bus cycle Note The first beat of any wri...

Страница 743: ...hows a 32 bit read from an 8 bit device with burst inhibited The transfer results in four individual transfers The transfer size is driven at 32 bit 00 during the first transfer and at byte 01 during...

Страница 744: ...32 bit Read Burst Inhibited from 8 Bit Port No Wait States The following figure shows a 32 bit write to an 8 bit device with burst inhibited The transfer results in four individual transfers The trans...

Страница 745: ...ort No Wait States The following figure illustrates another read burst transfer but in this case a wait state is added between individual beats Note CSCRn WS determines the number of wait states in th...

Страница 746: ...RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 49 32 bit Read Burst from 8 Bit Port 3 2 2 2 One Wait State The following figure illustrates a write burst transfer with one wait s...

Страница 747: ...ress setup and address hold Note In non multiplexed address data mode the address on FB_A increments only during internally terminated burst cycles CSCRn AA 1 The attached device must be able to accou...

Страница 748: ...Hold The following figure shows a write cycle with one clock of address setup and address hold Address Address Data TSIZ 11 AA 1 AA 0 AA 1 AA 0 Data Data Data Add 1 Add 2 Add 3 FB_CLK FB_A Y FB_D X FB...

Страница 749: ...one primary wait state Address Address Data TSIZ AA 1 AA 0 AA 1 AA 0 FB_CLK FB_A Y FB_D X FB_RW FB_TS FB_ALE FB_CSn FB_OEn FB_BE BWEn FB_TA FB_TSIZ 1 0 Figure 29 53 Read Bus Cycle with CSCRn EXTS 1 O...

Страница 750: ...register setting the valid bit The CSPMCR register is not required to be part of this procedure However it should only be configured when the FlexBus is idle The corresponding chip select can be vali...

Страница 751: ...g ISP of flash memory contents on a 32 bit general purpose micro controller Memory contents can be read erased and programmed from off chip in a compatible format to many stand alone flash memory chip...

Страница 752: ...t to boot from the flash memory after the memory has been configured 30 1 3 Modes of Operation The EzPort can operate in one of two different modes enabled or disabled Enabled When enabled the EzPort...

Страница 753: ...The following table contains a list of EzPort external signals and the following sections explain them in detail Table 30 1 EzPort External Signal Descriptions Name Description I O EZP_CK EzPort Cloc...

Страница 754: ...P_D is ignored 30 2 4 EzPort Serial Data Out EZP_Q Serial data out for data transfers EZP_Q is driven on the falling edge of EZP_CK It is tri stated unless EZP_CS is asserted and the EzPort is driving...

Страница 755: ...et 6 Note that the Flash will be in NVM Special mode restricting which types of commands can be executed through WRITE_FCCOB when security is enabled 30 3 1 Command Descriptions This section describes...

Страница 756: ...mmand is accepted while a write is in progress 0 Write is not in progress Accept any command 1 Write is in progress Only accept RDSR command 1 WEN Write enable Control bit that must be set before a wr...

Страница 757: ...tial address specified in the command word The initial address must be 32 bit aligned the two LSBs must be zero Data continues being returned for as long as the EzPort chip select EZP_CS is asserted w...

Страница 758: ...exRAM to be configured for traditional RAM operation By default after entering EzPort mode the FlexRAM is configured for traditional RAM operation If the user reconfigures FlexRAM for EEPROM operation...

Страница 759: ...it has been programmed by an external source This command is not accepted if the WIP bit is set in the EzPort status register 30 3 1 10 Write FCCOB Registers The Write FCCOB Registers WRFCCOB command...

Страница 760: ...eate data records in EEPROM flash memory By default after entering EzPort mode the FlexRAM is configured for traditional RAM operation and functions as direct RAM The user can alter the FlexRAM config...

Страница 761: ...ed This command is only applicable for devices with FlexRAM The Read FlexRAM at High Speed FAST_RDFLEXRAM is identical to the RDFLEXRAM command except for the inclusion of a dummy byte following the a...

Страница 762: ...mands 0x0080_0000 See device s Chip Configuration details FlexNVM READ FAST_READ SP SE BE 0x0000_0000 See device s Chip Configuration details FlexRAM RDFLEXRAM FAST_RDFLEXRAM WRFLEXRAM BE Flash Memory...

Страница 763: ...1 1 Features Features of the CRC module include Hardware CRC generator circuit using a 16 bit or 32 bit programmable shift register Programmable initial seed value and polynomial Option to transpose i...

Страница 764: ...diagram 31 1 3 Modes of operation Various MCU modes affect the CRC module s functionality 31 1 3 1 Run mode This is the basic mode of operation 31 1 3 2 Low power modes wait or stop Any CRC calculatio...

Страница 765: ...h MSB of data value written first After all data values are written the CRC result can be read from this data register In 16 bit CRC mode the CRC result is available in the LU and LL fields In 32 bit...

Страница 766: ...Register CRC_GPOLY This register contains the value of the polynomial for the CRC calculation The HIGH field contains the upper 16 bits of the CRC polynomial which are used only in 32 bit CRC mode Wr...

Страница 767: ...e for Read These bits identify the transpose configuration of the value read from the CRC data register Refer to the description of the transpose feature for the available transpose options 00 No tran...

Страница 768: ...ze the CRC module for a new CRC computation All other parameters must be set before programming the seed value and subsequent data values 31 3 2 CRC calculations In 16 bit and 32 bit CRC modes data va...

Страница 769: ...alues 7 Write data values into CRC HU HL LU LL A CRC is computed on every data value write and the intermediate CRC result is stored back into CRC HU HL LU LL 8 When all values have been written read...

Страница 770: ...occurs 2 CTRL TOT or CTRL TOTR is 01 Bits in a byte are transposed while bytes are not transposed reg 31 0 becomes reg 24 31 reg 16 23 reg 8 15 reg 0 7 15 15 8 7 0 0 7 8 31 31 24 23 16 16 23 24 Figure...

Страница 771: ...tion resides in the CRC HU HL fields The user software must account for this situation when reading the 16 bit CRC result so reading 32 bits is preferred 31 3 4 CRC result complement When the CTRL FXO...

Страница 772: ...Functional description K53 Sub Family Reference Manual Rev 6 Nov 2011 772 Freescale Semiconductor Inc...

Страница 773: ...tion of a set of specialized operations to improve the throughput of software based security encryption decryption operations and message digest functions The MMCAU supports acceleration of the DES 3D...

Страница 774: ...en the private APB interface and the CAU module Passes memory mapped commands and data on the APB to from the CAU 4 entry FIFO Contains commands and input operands plus the associated control captured...

Страница 775: ...ns The set of implemented algorithms provides excellent support for network security standards SSL IPsec Additionally using the MMCAU efficiently permits the implementation of any higher level functio...

Страница 776: ...contains multiple registers used by each of the supported algorithms The following table shows which registers are applicable to each supported algorithm and indicates the corresponding letter design...

Страница 777: ...set refers to the command code value for the CAU registers CAU memory map Absolute address hex Register name Width in bits Access Reset value Section page E008_1000 Status Register CAU_CASR 32 R W 200...

Страница 778: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R VER 0 DPE IC W Reset 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAU_CASR field descriptions Field Description 31 28 VER CAU version Indicat...

Страница 779: ...h offset E008_1002h CAU_CA1 is E008_1000h base 3h offset E008_1003h CAU_CA2 is E008_1000h base 4h offset E008_1004h CAU_CA3 is E008_1000h base 5h offset E008_1005h CAU_CA4 is E008_1000h base 6h offset...

Страница 780: ...alue The CAU requires a 15 bit command and optionally a 32 bit input operand for each CAU load PPB write The 15 bit command includes the 9 bit opcode plus other bits statically formed by the MMCAU tra...

Страница 781: ...15 MMCAU memory map 32 6 1 1 Direct Loads The MMCAU supports writing multiple commands in each 32 bit direct write operation Each 9 bit opcode also includes a valid bit Therefore one two or three com...

Страница 782: ...details are MMCAU base address 1 0 0 31 0 4 8 12 16 20 24 28 CAU_STR Rn Read address CAx 31 0 4 8 12 16 20 24 28 Read data Figure 32 18 Indirect store 32 6 2 MMCAU Integrity Checks If an illegal opera...

Страница 783: ...r termination Within the second 2 Kbyte region addr 11 1 of the address space only a 64 byte space is treated as a legal CAU store operation The allowable addresses are defined as addr 11 0 1000_10xx_...

Страница 784: ...interpreted as any CAU register CASR CAA CAn Table 32 15 CAU Commands Type Command Name Description CMD Operation 8 7 6 5 4 3 2 1 0 Direct load CNOP No Operation 0x000 Indirect load LDR Load Reg 0x01...

Страница 785: ...t load SHS Secure Hash Shift 0x130 CAA 5 CAA CAA CA0 CA0 CA1 CA1 30 CA2 CA2 CA3 CA3 CA4 Direct load MDS Message Digest Shift 0x140 CA3 CAA CAA CA1 CA1 CA2 CA2 CA3 Direct load SHS2 Secure Hash Shift 2...

Страница 786: ...s table shows an example Table 32 16 RADR Command Example Operand CAx Before CAx After 0x0102_0304 0xA0B0_C0D0 0xA4B3_C2D1 32 6 3 6 Add Register to Accumulator ADRA The ADRA command adds CAx to CAA an...

Страница 787: ...umn Operation AESC The AESC command performs the AES column operation on the contents of CAx then performs an exclusive or of that result with the source operand specified by the write data and stores...

Страница 788: ...e following source and destination designations CA0 C CA1 D CA2 L CA3 R If the IP bit is set DES initial permutation performs on CA2 and CA3 before the round operation If the FP bit is set DES final p...

Страница 789: ...t in CAA The specific hash function performed is based on the HFx field as defined in this table This table uses the following terms ROTRn CAx rotate CAx register right n times SHRn CAx shift CAx regi...

Страница 790: ...implementing MD5 The following source and destination assignments are made Register Value prior to command Value after command executes CA3 CA3 CA2 CA2 CA2 CA1 CA1 CA1 CAA CAA CAA CA3 32 6 3 22 Secur...

Страница 791: ...nd space movw fp lower16 MMCAU_PPB_INDIRECT fp MMCAU_PPB_INDIRECT movt fp upper16 MMCAU_PPB_INDIRECT movw ip lower16 MMCAU_PPB_DIRECT ip MMCAU_PPB_DIRECT movt ip upper16 MMCAU_PPB_DIRECT r3 mmcau_3_cm...

Страница 792: ...s set KSR1 0x02 key schedule right 1 bit set KSR2 0x03 key schedule right 2 bits DESK Field set DC 0x01 decrypt key schedule set CP 0x02 check parity HASH Functions Codes set HFF 0x0 MD5 F CA1 CA2 CA1...

Страница 793: ...PRNG to achieve true randomness and cryptographic strength The RNGB generates random numbers for secret keys per message secrets random challenges and other similar quantities used in cryptographic al...

Страница 794: ...or its seed 33 2 Modes of Operation The RNGB operates in the following modes 33 2 1 Self Test Mode In this mode the RNGB performs a self test of the statistical counters and the PRNG algorithm to veri...

Страница 795: ...quickly creates computationally random data that is derived by the initial seed produced in seed generation mode During random number generation a new 160 bit random number is generated whenever the...

Страница 796: ...he RNGB It consists of the RNG type and major and minor revision numbers Address RNG_VER is 400A_0000h base 0h offset 400A_0000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...

Страница 797: ...is self clearing 0 Do not clear errors and interrupt 1 Clear errors and interrupt 4 CI Clear interrupt Clears the RNGB interrupt if an error is not present This bit is self clearing 0 Do not clear in...

Страница 798: ...0 0 0 0 0 0 0 0 0 RNG_CR field descriptions Field Description 31 10 Reserved This read only field is reserved and always has the value zero Reserved must be cleared 9 7 Reserved This read only field i...

Страница 799: ...seed whenever one is needed This allows software to never use the RNG_CMD GS although it is still possible A new seed is needed whenever the RNG_SR RS is set 0 Do not enable automatic reseeding 1 Enab...

Страница 800: ...or fail status of the various statistics tests on the last seed generated Bit 31 Long run test 34 Bit 30 Length 6 run test Bit 29 Length 5 run test Bit 28 Length 4 run test Bit 27 Length 3 run test Bi...

Страница 801: ...ocess not complete 1 Completed seed generation since the last reset 4 STDN Self test done Indicates the self test is complete This bit is cleared by hardware reset or a new self test is initiated by s...

Страница 802: ...be cleared 4 FUFE FIFO underflow error Indicates the RNGB has experienced a FIFO underflow condition resulting in the last random data read being unreliable This bit can be masked by RNG_CR FUFMOD an...

Страница 803: ...tput FIFO RNG_OUT The RNGBOUT provides temporary storage for random data generated by the RNGB This allows the user to read multiple random longwords back to back A read of this address when the FIFO...

Страница 804: ...e simultaneous reseed LFSRs The entropy stored in this 128 bit LFSR and 128 bit shift register is added directly into the XKEY structure via the RNGB XSEED generator whenever reseeding is required 33...

Страница 805: ...are reset may be performed at any time 33 4 4 RNG Interrupts There is a single RNG interrupt generated to the processor s interrupt controller The source of the interrupt is determined by reading the...

Страница 806: ...R FUFE MASKERR FIFO read while empty 33 5 Initialization Application Information This section describes the module initialization 33 5 1 Manual Seeding The intended general operation of the RNGB is as...

Страница 807: ...ing and the desired functionality 3 Wait for interrupt to indicate completion of first seed 4 Poll RNG_SR for FIFO level 5 Read available random data from output FIFO 6 Repeat steps 4 and 5 as needed...

Страница 808: ...Initialization Application Information K53 Sub Family Reference Manual Rev 6 Nov 2011 808 Freescale Semiconductor Inc...

Страница 809: ...e Linear successive approximation algorithm with up to 16 bit resolution Up to 4 pairs of differential and 24 single ended external analog inputs Output modes differential 16 bit 13 bit 11 bit and 9 b...

Страница 810: ...Automatic compare with interrupt for less than greater than or equal to within range or out of range programmable value Temperature sensor Hardware average function Selectable voltage reference extern...

Страница 811: ...nitialize sample convert transf e r abort CLPx PG MG PG MG CLPx Calibration OFS CALF CAL SC3 C V1 ACFGT ACREN D Formatting Averager AVGE AVGS ADCOFS V REFSH V REFSL SC2 CFG1 CFG2 DADP2 DADM2 PGA PGA V...

Страница 812: ...ly available connect the VSSA pin to the same voltage potential as VSS 34 2 3 Voltage reference select VREFSH and VREFSL are the high and low reference voltages for the converter The ADC can be config...

Страница 813: ...provide the most accurate analog to digital readings A differential input is selected for conversion through the ADCH channel select bits when the DIFF bit in the SC1n register bit is high All DADPx...

Страница 814: ...ide general calibration value register ADC0_CLPD 32 R W 0000_000Ah 34 3 11 829 4003_B038 ADC plus side general calibration value register ADC0_CLPS 32 R W 0000_0020h 34 3 12 830 4003_B03C ADC plus sid...

Страница 815: ...register 2 ADC1_CFG2 32 R W 0000_0000h 34 3 3 821 400B_B010 ADC data result register ADC1_RA 32 R 0000_0000h 34 3 4 822 400B_B014 ADC data result register ADC1_RB 32 R 0000_0000h 34 3 4 822 400B_B018...

Страница 816: ...3 22 836 400B_B064 ADC minus side general calibration value register ADC1_CLM2 32 R W 0000_0080h 34 3 23 836 400B_B068 ADC minus side general calibration value register ADC1_CLM1 32 R W 0000_0040h 34...

Страница 817: ...2 1 0 R 0 COCO AIEN DIFF ADCH W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 ADCx_SC1n field descriptions Field Description 31 8 Reserved This read only field is reserved and always has the value zero 7 COCO...

Страница 818: ...t 00001 When DIFF 0 DADP1 is selected as input when DIFF 1 DAD1 is selected as input 00010 When DIFF 0 DADP2 is selected as input when DIFF 1 DAD2 is selected as input 00011 When DIFF 0 DADP3 is selec...

Страница 819: ...bled 34 3 2 ADC configuration register 1 ADCx_CFG1 CFG1 register selects the mode of operation clock source clock divide and configure for low power or long sample time Addresses ADC0_CFG1 is 4003_B00...

Страница 820: ...2 MODE Conversion mode selection MODE bits are used to select the ADC resolution mode 00 When DIFF 0 It is single ended 8 bit conversion when DIFF 1 it is differential 9 bit conversion with 2 s comple...

Страница 821: ...nels 0 ADxxa channels are selected 1 ADxxb channels are selected 3 ADACKEN Asynchronous clock output enable ADACKEN enables the ADC s asynchronous clock source and the clock source output regardless o...

Страница 822: ...he data result registers Rn contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register SC1A SC1n For every status and channel control regi...

Страница 823: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 D W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCx_Rn field descriptions Field De...

Страница 824: ...31 16 Reserved This read only field is reserved and always has the value zero 15 0 CV Compare value 34 3 6 Status and control register 2 ADCx_SC2 The SC2 register contains the conversion active hardw...

Страница 825: ...pon the value of ACREN The ACFE bit must be set for ACFGT to have any effect 0 Configures less than threshold outside range not inclusive and inside range not inclusive functionality based on the valu...

Страница 826: ...0 0 0 0 0 0 0 0 0 0 0 ADCx_SC3 field descriptions Field Description 31 8 Reserved This read only field is reserved and always has the value zero 7 CAL Calibration CAL begins the calibration sequence w...

Страница 827: ...DC average result 00 4 samples averaged 01 8 samples averaged 10 16 samples averaged 11 32 samples averaged 34 3 8 ADC offset correction register ADCx_OFS The ADC offset correction register OFS contai...

Страница 828: ...base 2Ch offset 400B_B02Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ADCx...

Страница 829: ...alibration values of varying widths CLP0 5 0 CLP1 6 0 CLP2 7 0 CLP3 8 0 CLP4 9 0 CLPS 5 0 and CLPD 5 0 CLPx are automatically set once the self calibration sequence is done CAL is cleared If these reg...

Страница 830: ...ays has the value zero 5 0 CLPS Calibration value 34 3 13 ADC plus side general calibration value register ADCx_CLP4 For more information refer to CLPD register description Addresses ADC0_CLP4 is 4003...

Страница 831: ...value zero 8 0 CLP3 Calibration value 34 3 15 ADC plus side general calibration value register ADCx_CLP2 For more information refer to CLPD register description Addresses ADC0_CLP2 is 4003_B000h base...

Страница 832: ...ways has the value zero 6 0 CLP1 Calibration value 34 3 17 ADC plus side general calibration value register ADCx_CLP0 For more information refer to CLPD register description Addresses ADC0_CLP0 is 400...

Страница 833: ...24 Reserved This read only field is reserved and always has the value zero 23 PGAEN PGA enable 0 PGA disabled 1 PGA enabled 22 Reserved This read only field is reserved and always has the value zero 2...

Страница 834: ...CLMx are automatically set once the self calibration sequence is done CAL is cleared If these registers are written by the user after calibration the linearity error specifications may not be met Add...

Страница 835: ...value zero 5 0 CLMS Calibration value 34 3 21 ADC minus side general calibration value register ADCx_CLM4 For more information refer to CLMD register description Addresses ADC0_CLM4 is 4003_B000h bas...

Страница 836: ...ways has the value zero 8 0 CLM3 Calibration value 34 3 23 ADC minus side general calibration value register ADCx_CLM2 For more information refer to CLMD register description Addresses ADC0_CLM2 is 40...

Страница 837: ...value zero 6 0 CLM1 Calibration value 34 3 25 ADC minus side general calibration value register ADCx_CLM0 For more information refer to CLMD register description Addresses ADC0_CLM0 is 4003_B000h bas...

Страница 838: ...abled AIEN 1 The ADC module has the capability of automatically comparing the result of a conversion with the contents of the compare value registers The compare function is enabled by setting the ACF...

Страница 839: ...hat when the ADACK clock source is selected it is not required to be active prior to conversion start When it is selected and it is not active prior to a conversion start ADACKEN 0 the asynchronous cl...

Страница 840: ...ising edge of ADHWT after a hardware trigger select event ADHWTSn has occurred If a conversion is in progress when a rising edge of a trigger occurs the rising edge is ignored In continuous convert co...

Страница 841: ...d compare value 34 4 5 1 Initiating conversions A conversion is initiated Following a write to SC1A register with ADCH bits not all 1 s if software triggered operation is selected ADTRG 0 Following a...

Страница 842: ...OCO bit sets only if the last of the selected number of conversions is completed If the compare function is enabled the respective COCO bit sets and conversion result data is transferred only if the c...

Страница 843: ...the asynchronous clock output is enabled ADACKEN 1 it remains active regardless of the state of the ADC or the MCU power mode Power consumption when the ADC is active can be reduced by setting ADLPC...

Страница 844: ...d to Rn upon completion of the conversion algorithm If the bus frequency is less than the fADCK frequency precise sample time for continuous conversions cannot be guaranteed when short sample is enabl...

Страница 845: ...diff 34 ADCK cycles Table 34 110 Long sample time adder LSTAdder ADLSMP ADLSTS Long sample time adder LSTAdder 0 xx 0 ADCK cycles 1 00 20 ADCK cycles 1 01 12 ADCK cycles 1 10 6 ADCK cycles 1 11 2 ADCK...

Страница 846: ...erated using the parameters listed in the proceeding table Therefore for a bus clock equal to 8 MHz and an ADCK equal to 8 MHz the resulting conversion time is 3 75 s 34 4 5 6 2 Long conversion time c...

Страница 847: ...rmation provided in Table 34 107 through Table 34 111 The table below list the variables of Figure 34 95 Table 34 114 Typical conversion time Variable Time SFCAdder 5 ADCK cycles 5 bus clock cycles Av...

Страница 848: ...d by two compare values The compare mode is determined by ACFGT ACREN and the values in the compare value registers CV1 and CV2 After the input is sampled and converted the compare values CV1 and CV2...

Страница 849: ...when the compare condition is met 34 4 7 Calibration function The ADC contains a self calibration function that is required to achieve the specified accuracy Calibration must be run or valid calibrati...

Страница 850: ...not set the automatic calibration routine completed successfully To complete calibration the user must generate the gain calibration values using the following procedure 1 Initialize clear a 16 bit va...

Страница 851: ...t which maps to bit D 8 For 16 bit differential mode all bits OFS 15 0 are directly subtracted from the conversion result data D 15 0 In 16 bit single ended mode there is no bit in the offset correcti...

Страница 852: ...provides an approximate transfer function of the temperature sensor m Figure 34 96 Approximate transfer function of the temperature sensor where VTEMP is the voltage of the temperature sensor channel...

Страница 853: ...enabled the COCO will set and generate an interrupt if enabled when the selected number of conversions are completed If the compare function is enabled the COCO will set and generate an interrupt if e...

Страница 854: ...ed only if the compare conditions are met If a single conversion is selected and the compare is not true the ADC will return to its idle state and cannot wake the MCU from Normal Stop mode unless a ne...

Страница 855: ...tware and compare function options if enabled 4 Update status and control register 3 SC3 to select whether conversions will be continuous or completed only once ADCO and to select whether to perform h...

Страница 856: ...disabled Bit 4 ACFGT 0 Not used in this example Bit 3 ACREN 0 Compare range disabled Bit 2 DMAEN 0 DMA request disabled Bit 1 0 REFSEL 00 Selects default voltage reference pin pair External pins VREFH...

Страница 857: ...ions requiring an ADC 34 6 1 External pins and routing The following sections discuss the external pins associated with the ADC module and how they should be used for best results 34 6 1 1 Analog supp...

Страница 858: ...LTL These voltage references are selected using the REFSEL bits in the SC2 register The alternate VALTH and VALTL voltage reference pair may select additional external pins or internal sources dependi...

Страница 859: ...REFL If the input is equal to or exceeds VREFH the converter circuit converts the signal to 0xFFF full scale 12 bit representation 0x3FF full scale 10 bit representation or 0xFF full scale 8 bit repre...

Страница 860: ...8 bit mode 10 in 10 bit mode 12 in 12 bit mode or 16 in 16 bit mode 34 6 2 3 Noise induced errors System noise that occurs during the sample or conversion process can affect the accuracy of the conver...

Страница 861: ...1 LSB one time error Reduce the effect of synchronous noise by operating off the asynchronous clock ADACK and averaging Noise that is synchronous to ADCK cannot be averaged out 34 6 2 4 Code width and...

Страница 862: ...is error is defined as the worst case difference between the actual code width and the ideal code width for all conversions Integral non linearity INL This error is defined as the highest value the ab...

Страница 863: ...s defined as when except for code jitter the converter converts to a lower code for a higher input voltage Missing codes are those values never converted for any input value In 8 bit or 10 bit mode th...

Страница 864: ...Application information K53 Sub Family Reference Manual Rev 6 Nov 2011 864 Freescale Semiconductor Inc...

Страница 865: ...supply voltage The 6 bit DAC is 64 tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed The 64 tap resistor ladder network divid...

Страница 866: ...functions Two software selectable performance levels Shorter propagation delay at the expense of higher power Low power with longer propagation delay Support DMA transfer A comparison event can be sel...

Страница 867: ...ly range 35 5 CMP DAC and ANMUX Diagram The following figure shows the block diagram for the High Speed Comparator Digital to Analog Converter and Analog MUX modules Chapter 35 Comparator CMP K53 Sub...

Страница 868: ...rence Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Reference Input 5 Reference Input 6 INP INM Sample Input Figure 35 1 CMP DAC and ANMUX Blocks Diagram 35 6 CMP Block Diagram The fol...

Страница 869: ...E 1 the comparator output will be sampled on every bus clock when WINDOW 1 to generate COUTA Sampling does NOT occur when WINDOW 0 The Filter Block is bypassed when not in use The Filter Block acts as...

Страница 870: ...0_SCR 8 R W 00h 35 7 4 874 4007_3004 DAC Control Register CMP0_DACCR 8 R W 00h 35 7 5 875 4007_3005 MUX Control Register CMP0_MUXCR 8 R W 00h 35 7 6 876 4007_3008 CMP Control Register 0 CMP1_CR0 8 R W...

Страница 871: ...ved and always has the value zero 6 4 FILTER_CNT Filter Sample Count These bits represent the number of consecutive samples that must agree prior to the comparator ouput filter accepting a new output...

Страница 872: ...ription 7 SE Sample Enable At any given time either SE or WE can be set If a write to this register attempts to set both then SE is set and WE is cleared However avoid writing ones to both bit locatio...

Страница 873: ...Pin Enable 0 The comparator output CMPO is not available on the associated CMPO output pin 1 The comparator output CMPO is available on the associated CMPO output pin 0 EN Comparator Module Enable The...

Страница 874: ...ue zero 6 DMAEN DMA Enable Control The DMAEN bit enables the DMA transfer triggered from the CMP module When this bit is set a DMA request is asserted when the CFR or CFF bit is set 0 DMA disabled 1 D...

Страница 875: ...bit is set when a falling edge on COUT has been detected The CFF bit is cleared by writing a logic one to the bit During Stop modes CFF can be programmed as either edge or level sensitive via the SME...

Страница 876: ...07_3008h base 5h offset 4007_300Dh CMP2_MUXCR is 4007_3010h base 5h offset 4007_3015h Bit 7 6 5 4 3 2 1 0 Read PEN MEN PSEL MSEL Write Reset 0 0 0 0 0 0 0 0 CMPx_MUXCR field descriptions Field Descrip...

Страница 877: ...ts down to prevent itself from becoming a noise generator 000 IN0 001 IN1 010 IN2 011 IN3 100 IN4 101 IN5 110 IN6 111 IN7 35 8 CMP Functional Description The Comparator can be used to compare two anal...

Страница 878: ...the input voltages are not valid This is especially useful when implementing zero crossing detection for certain PWM applications The comparator filter and sampling features can be combined as shown i...

Страница 879: ...ll other combinations of CR1 EN CR1 WE CR1 SE CR0 FILTER_CNT and FPR FILT_PER are illegal For cases where a comparator is used to drive a fault input for example for a motor control module such as FTM...

Страница 880: ...ion section for the source of sample window input The analog comparator block is powered and active CMPO may be optionally inverted but is not subject to external sampling or filtering Both Window Con...

Страница 881: ...ock is powered and active The path from analog inputs to COUTA is combinational unclocked Windowing Control is completely bypassed COUTA is sampled whenever a rising edge is detected on the Filter Blo...

Страница 882: ...rived 35 8 1 4 Sampled Filtered Mode s 4A 4B In Sampled Filtered mode the analog comparator block is powered and active The path from analog inputs to COUTA is combinational unclocked Windowing Contro...

Страница 883: ...bus clock COS IER F CFR F WINDOW SAMPLE 1 0 EN PMODE HYSTCTR 1 0 Polarity Select Window Control Filter Block Interrupt Control Clock Prescaler divided bus clock CMPO 0x01 Figure 35 30 Sampled Filtere...

Страница 884: ...ILTER_CNT is now greater than 1 which activates filter operation 35 8 1 5 Windowed Mode s 5A 5B The following figure illustrates comparator operation in the windowed mode ignoring latency of the analo...

Страница 885: ...X COS FILT_PER 0 FILT_PER bus clock COS 0x01 IER F CFR F WINDOW SAMPLE Polarity Select Window Control Filter Block Interrupt Control divided bus clock Clock Prescaler CMPO Figure 35 33 Windowed Mode F...

Страница 886: ...on the sampling rate and window placement COUT may not see zero crossing events detected by the analog comparator Sampling period and or window placement must be carefully considered for a given appli...

Страница 887: ...value is held when WINDOW 0 IRQ INTERNAL BUS EN PMODE HYSCTR 1 0 INP INM FILTER_CNT INV COUT COUT OPE SE CMPO to PAD TO OTHER SOC FUNCTIONS COUTA 0 1 WE 1 0 SE 0 CGMUX COS FILT_PER 0 1 FILT_PER bus c...

Страница 888: ...e MCU can be brought out of the low leakage mode if a compare event occurs and the CMP interrupt is enabled After wakeup from low leakage modes the CMP module is in the reset state except for the SCR...

Страница 889: ...ges differ by less than the offset voltage of the differential comparator 35 8 4 1 Enabling Filter Modes Filter Modes are enabled by setting CR0 FILTER_CNT greater than 0x01 and setting FPR FILT_PER t...

Страница 890: ...ked by noise The values of FPR FILT_PER or SAMPLE period and CR0 FILTER_CNT must also be traded off against the desire for minimal latency in recognizing actual comparator output transitions The proba...

Страница 891: ...e CMP generates a CPU interrupt if there is a change on the COUT When DMA support set SCR DMAEN enables and the interrupt enables set SCR IER or SCR IEF or both the corresponding change on COUT forces...

Страница 892: ...ltage source as supply reference of 64 tap resistor ladder Vin2 should be used to connect to alternate voltage source or primary source if alternate voltage source is not available 35 13 DAC Resets Th...

Страница 893: ...35 15 DAC Interrupts This module has no interrupts Chapter 35 Comparator CMP K53 Sub Family Reference Manual Rev 6 Nov 2011 Freescale Semiconductor Inc 893...

Страница 894: ...DAC Interrupts K53 Sub Family Reference Manual Rev 6 Nov 2011 894 Freescale Semiconductor Inc...

Страница 895: ...to the analog comparator Op Amps ADC or other peripherals 36 2 Features The DAC module features include On chip programmable reference generator output voltage output from 1 4096 Vin to Vin step is 1...

Страница 896: ...re 36 1 DAC Block Diagram 36 4 Memory Map Register Definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital to analog functions The address...

Страница 897: ...0 400C_C009 DAC Data High Register DAC0_DAT4H 8 R W 00h 36 4 2 901 400C_C00A DAC Data Low Register DAC0_DAT5L 8 R W 00h 36 4 1 900 400C_C00B DAC Data High Register DAC0_DAT5H 8 R W 00h 36 4 2 901 400C...

Страница 898: ...DAT14L 8 R W 00h 36 4 1 900 400C_C01D DAC Data High Register DAC0_DAT14H 8 R W 00h 36 4 2 901 400C_C01E DAC Data Low Register DAC0_DAT15L 8 R W 00h 36 4 1 900 400C_C01F DAC Data High Register DAC0_DAT...

Страница 899: ...900 400C_D00D DAC Data High Register DAC1_DAT6H 8 R W 00h 36 4 2 901 400C_D00E DAC Data Low Register DAC1_DAT7L 8 R W 00h 36 4 1 900 400C_D00F DAC Data High Register DAC1_DAT7H 8 R W 00h 36 4 2 901 4...

Страница 900: ..._DAT15H 8 R W 00h 36 4 2 901 400C_D020 DAC Status Register DAC1_SR 8 R 02h 36 4 3 901 400C_D021 DAC Control Register DAC1_C0 8 R W 00h 36 4 4 902 400C_D022 DAC Control Register 1 DAC1_C1 8 R W 00h 36...

Страница 901: ...it Writing one has no effect After reset DACBFRPTF is set and can be cleared by software if needed The flags are set only when the data buffer status is changed Addresses DAC0_SR is 400C_C000h base 2...

Страница 902: ...Generator operation 0 The DAC system is disabled 1 The DAC system is enabled 6 DACRFS DAC Reference Select 0 The DAC selets DACREF_1 as the reference voltage 1 The DAC selets DACREF_2 as the reference...

Страница 903: ..._D022h Bit 7 6 5 4 3 2 1 0 Read DMAEN 0 DACBFWM DACBFMD DACBFEN Write Reset 0 0 0 0 0 0 0 0 DACx_C1 field descriptions Field Description 7 DMAEN DMA enable select 0 DMA disabled 1 DMA enabled When DMA...

Страница 904: ...DACx_C2 field descriptions Field Description 7 4 DACBFRP DAC buffer read pointer These 4 bits keep the current value of the buffer read pointer 3 0 DACBFUP DAC buffer upper limit These 4 bits select...

Страница 905: ...ointer bottom position flag is set when the DAC buffer read pointer reaches the DAC buffer upper limit DACBFRP DACBFUP The DAC read pointer top position flag is set when the DAC read pointer is equal...

Страница 906: ...A done signal clears the DMA request The status register flags are still set and are cleared automatically when the DMA completes 36 5 3 Resets During reset the DAC is configured in the default mode D...

Страница 907: ...odes is chip specific For module to core mode assignments see the chapter that describes how modules are configured Chapter 36 12 bit Digital to Analog Converter DAC K53 Sub Family Reference Manual Re...

Страница 908: ...Functional Description K53 Sub Family Reference Manual Rev 6 Nov 2011 908 Freescale Semiconductor Inc...

Страница 909: ...as several timing and control settings that can be software configured depending on the application requirements Timing and control consists of registers and control logic for Amplifier gain programma...

Страница 910: ...put 3 Negative Input 2 Negative Input 1 Positive Input 1 Positive Input 2 Positive Input 3 Positive Input 4 Positive Input 5 Positive Input 6 Negative Input 0 Positive Input 0 Negative Input 7 Positiv...

Страница 911: ...A mode 01 10 9 Inverting PGA mode 01 01 10 Inverting PGA mode 01 11 11 Inverting PGA mode 01 00 010 4 Inverting PGA mode 01 10 5 Inverting PGA mode 01 01 6 Inverting PGA mode 01 11 7 Inverting PGA mod...

Страница 912: ...verting PGA mode 11 01 11 Non inverting PGA mode 11 11 12 Non inverting PGA mode 11 00 010 5 Non inverting PGA mode 11 10 6 Non inverting PGA mode 11 01 7 Non inverting PGA mode 11 11 8 Non inverting...

Страница 913: ...erminal I VOUTx Amplifier output terminal O 37 2 1 INPx The positive input terminal to the amplifier This is an analog input terminal See the Data Sheet for the value of input offset current and input...

Страница 914: ...7 3 2 915 400F_5802 Control Register 2 OPAMP1_C2 8 R W 00h 37 3 3 916 37 3 1 Control Register 0 OPAMPx_C0 Addresses OPAMP0_C0 is 400F_5000h base 0h offset 400F_5000h OPAMP1_C0 is 400F_5800h base 0h of...

Страница 915: ...n inverting PGA 37 3 2 Control Register 1 OPAMPx_C1 Addresses OPAMP0_C1 is 400F_5000h base 1h offset 400F_5001h OPAMP1_C1 is 400F_5800h base 1h offset 400F_5801h Bit 7 6 5 4 3 2 1 0 Read 0 AMPRF AMPRI...

Страница 916: ...these inputs 000 Positive input 0 001 Positive input 1 010 Positive input 2 011 Positive input 3 100 Positive input 4 101 Positive input 5 110 Positive input 6 111 Positive input 7 3 Reserved This rea...

Страница 917: ...nput 5 Negative Input 4 Negative Input 3 Negative Input 2 Negative Input 1 Positive Input 1 Positive Input 2 Positive Input 3 Positive Input 4 Positive Input 5 Positive Input 6 Negative Input 0 Positi...

Страница 918: ...Positive Input 6 Negative Input 0 Positive Input 0 Negative Input 7 Positive Input 7 Mode select Programmable resistor network MODE AMPRI Figure 37 12 Operational Amplifier Block Diagram in Buffered...

Страница 919: ...tive Input 2 Positive Input 3 Positive Input 4 Positive Input 5 Positive Input 6 Negative Input 0 Positive Input 0 Negative Input 7 Positive Input 7 Mode select Programmable resistor network MODE AMPR...

Страница 920: ...Functional Description K53 Sub Family Reference Manual Rev 6 Nov 2011 920 Freescale Semiconductor Inc...

Страница 921: ...uirements Timing and control consists of registers and control logic for operation in low power modes 38 1 1 Features Features include On chip generation of bias voltages Low power low voltage CMOS te...

Страница 922: ...mplifier positive input terminal I inn_3v Amplifier negative input terminal I out_3v Amplifier output terminal O 38 1 5 inp_3v The positive input terminal to the amplifier This is an analog input term...

Страница 923: ...lifier is disabled and not powered 1 TRIAMP system is enabled In this mode the amplifier is powered and enabled 6 LPEN Low Power Enable The LPEN bit is power level control bit Refer to the device data...

Страница 924: ...on supply is 3 V diagram of the TRIAMP module NOTE An ideal operational amplifier model is shown out_3v inn_3v inp_3v photodiode off_chip Iphoto PAD Vdac 0 R1 P A OUT Iphoto Rf Figure 38 5 Zero Biased...

Страница 925: ...oto Rf Vdac 1 nA 1M 0 2 0 201 V 10 nA 1M 0 2 0 210 V 100 nA 1M 0 2 0 3 V 1 A 1M 0 2 1 2 V 10 nA 100 k 0 2 0 201 V 100 nA 100 k 0 2 0 21 V 1 A 100 k 0 2 0 3 V 10 A 100 k 0 2 1 2 V 100 nA 10 k 0 2 0 201...

Страница 926: ...Functional Description K53 Sub Family Reference Manual Rev 6 Nov 2011 926 Freescale Semiconductor Inc...

Страница 927: ...rimmed in 0 5 mV steps The VREFV1 can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC DAC or CMP The...

Страница 928: ...ipherals such as ADCs and DACs Refer to the chip configuration chapter for a description of these options The reference voltage is output on a dedicated output pin when the VREF is enabled The Voltage...

Страница 929: ...odes Note however that the accuracy of the output voltage will be reduced by as much as several mVs when the VREF regulator is not used NOTE The assignment of module modes to core modes is chip specif...

Страница 930: ...TRM field descriptions Field Description 7 Reserved This field is reserved Upon reset this value is loaded with a factory trim value This bit must always be written with the original reset value 6 Res...

Страница 931: ...nstant internal voltage supply in order to reduce the sensitivity to external supply noise and variation The VREF regulator must not be enabled when entering VLPR VLPW or VLPS modes 0 Internal 1 75 V...

Страница 932: ...ty 0 X Voltage Reference disabled Off 1 00 Voltage Reference enabled only the VREF bandgap is on Startup and standby 1 01 Reserved Reserved 1 10 Voltage Reference enabled VREF bandgap and tight regula...

Страница 933: ...39 3 2 2 SC MODE_LV 01 Reserved 39 3 2 3 SC MODE_LV 10 The tight regulation buffer is enabled to generate a buffered 1 2 V voltage to VREF_OUT If this mode is entered from the standby mode SC MODE_LV...

Страница 934: ...fied in the appropriate device data sheet Also there will be some settling time when a step change of the load current is applied to the VREF_OUT pin When the 1 75V VREF regulator is disabled the VREF...

Страница 935: ...n optionally provides pulse outputs Pulse Out s that are used as the sample window in the CMP block 40 1 1 Features Up to 15 trigger input sources and software trigger source Up to eight configurable...

Страница 936: ...tputs pulse out s Pulse out s can be enabled or disabled independently Programmable pulse width NOTE The number of PDB input and output triggers are chip specific Refer to the Chip Configuration infor...

Страница 937: ...to back operation acknowledgment connections are chip specific For implementation refer to the Chip Configuration information 40 1 4 DAC External Trigger Input Connections The implementation of DAC e...

Страница 938: ...14 SWTRIG TRIGSEL DACINTx DAC Interval Counter x EXTx DAC ext trigger input x DAC interval trigger x TOEx PDBIDLY PDB interrupt TOEx POyDLY2 POyDLY1 Pulse Generation Pulse Out y PDBPOEN y Pulse Out y...

Страница 939: ...us register and the counting is restarted This enables a continuous stream of pre triggers trigger outputs as a result of a single trigger input event Enabled Bypassed The pre trigger and trigger outp...

Страница 940: ...Control Register 1 PDB0_CH1C1 32 R W 0000_0000h 40 3 5 945 4003_603C Channel n Status Register PDB0_CH1S 32 w1c 0000_0000h 40 3 6 946 4003_6040 Channel n Delay 0 Register PDB0_CH1DLY0 32 R W 0000_000...

Страница 941: ...gister value after 1 is written to LDOK 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK 11 The internal regist...

Страница 942: ...clock divided by 64 times of the multiplication factor selected by MULT 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT 11 8 TRGSEL Trigger I...

Страница 943: ...iting 1 to this bit updates the internal registers of MOD IDLY CHnDLYm DACINTx and POyDLY with the values written to their buffers The MOD IDLY CHnDLYm DACINTx and POyDLY will take effect according to...

Страница 944: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDBx_CNT field descriptions Field Description 31 16 Reserved This read only field is reserved and always has the value zero 15 0 CNT PDB Counter These r...

Страница 945: ...ted in this MCU Back to back operation enables the ADC conversions complete to trigger the next PDB channel pre trigger and trigger output so that the ADC conversions can be triggered on next set of c...

Страница 946: ...lways has the value zero 23 16 CF PDB Channel Flags The CF m bit is set when the PDB counter matches the CHnDLYm Write 0 to clear these bits 15 8 Reserved This read only field is reserved and always h...

Страница 947: ...t is effective for the current PDB cycle 40 3 8 Channel n Delay 1 Register PDBx_CHDLY1 Addresses PDB0_CH0DLY1 is 4003_6000h base 1Ch offset 4003_601Ch PDB0_CH1DLY1 is 4003_6000h base 44h offset 4003_6...

Страница 948: ...software trigger is selected and SWTRIG is written with 1 1 DAC external trigger input enabled DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger 0 TOE...

Страница 949: ...0 0 0 0 0 PDBx_POEN field descriptions Field Description 31 8 Reserved This read only field is reserved and always has the value zero 7 0 POEN PDB Pulse Out Enable These bits enable the pulse output...

Страница 950: ...at which changes in the pre trigger m output signal is initiated The time is defined as Trigger input event to pre trigger m prescaler X multiplication factor X delay m 2 peripheral clock cycles Add...

Страница 951: ...r output starts an ADC conversion an internal lock associated with the corresponding pre trigger is activated The lock becomes inactive when the corresponding ADCnSC1 COCO is set or the corresponding...

Страница 952: ...ACINTx register the DAC interval trigger x output generates a pulse of one peripheral clock cycle width to update the DACx If DACINTCx EXT is set the DAC interval counter is bypassed and the interval...

Страница 953: ...he value set in POyDLY DLY1 the Pulse Out goes high when the counter reaches POyDLY DLY2 it goes low POyDLY DLY2 can be set either greater or less than POyDLY DLY1 Because the PDB counter is shared by...

Страница 954: ...he MOD register value after 1 is written to SC LDOK 10 A trigger input event is detected after 1 is written to SC LDOK 11 Either the PDB counter reaches the MOD register value or a trigger input event...

Страница 955: ...If SC DMAEN is set PDB can generate DMA transfer request when SC PDBIF is set When DMA is enabled the PDB interrupt will not be issued 40 5 Application Information 40 5 1 Impact of Using the Prescale...

Страница 956: ...as detected are mod 4 and so forth If the applications need a really long delay value and use 128 then the resolution would be limited to 128 peripheral clock cycles Therefore use the lowest possible...

Страница 957: ...utions and power conversion yet providing low cost and backwards compatibility with the TPM module Several key enhancements are made signed up counter deadtime insertion hardware fault control inputs...

Страница 958: ...n be the system clock the fixed frequency clock or an external clock Fixed frequency clock is an additional clock input to allow the selection of an on chip clock source other than the system clock Se...

Страница 959: ...isters Backwards compatible with TPM Testing of input captures for a stuck at zero and one conditions Dual edge capture for pulse and period width measurement Quadrature decoder with input filters rel...

Страница 960: ...s the channel number 0 7 The following figure shows the FTM structure The central component of the FTM is the 16 bit counter with programmable initial and final values and its counting can be up or up...

Страница 961: ...C7V CH6IE CH6F CH1IE CH0IE CH7IE CH7F CH1F CH0F channel 0 interrupt channel 1 interrupt channel 6 interrupt channel 7 interrupt channel 7 match trigger channel 6 output signal channel 6 match trigger...

Страница 962: ...clock frequency The FTM counter prescaler selection and settings are also used when an external clock is selected 41 2 2 CHn FTM Channel n I O Pin Each FTM channel can be configured to operate either...

Страница 963: ...gnal is one of the signals that control the FTM counter increment or decrement in the quadrature decoder mode Quadrature Decoder Mode 41 3 Memory Map and Register Definition This section provides a de...

Страница 964: ...00_0000h 41 3 6 973 4003_8018 Channel n Value FTM0_C1V 32 R W 0000_0000h 41 3 7 976 4003_801C Channel n Status and Control FTM0_C2SC 32 R W 0000_0000h 41 3 6 973 4003_8020 Channel n Value FTM0_C2V 32...

Страница 965: ...Function for Linked Channels FTM0_COMBINE 32 R W 0000_0000h 41 3 14 987 4003_8068 Deadtime Insertion Control FTM0_DEADTIME 32 R W 0000_0000h 41 3 15 992 4003_806C FTM External Trigger FTM0_EXTTRIG 32...

Страница 966: ...973 4003_9018 Channel n Value FTM1_C1V 32 R W 0000_0000h 41 3 7 976 4003_901C Channel n Status and Control FTM1_C2SC 32 R W 0000_0000h 41 3 6 973 4003_9020 Channel n Value FTM1_C2V 32 R W 0000_0000h 4...

Страница 967: ...7 4003_9068 Deadtime Insertion Control FTM1_DEADTIME 32 R W 0000_0000h 41 3 15 992 4003_906C FTM External Trigger FTM1_EXTTRIG 32 R W 0000_0000h 41 3 16 993 4003_9070 Channels Polarity FTM1_POL 32 R W...

Страница 968: ...Channel n Status and Control FTM2_C2SC 32 R W 0000_0000h 41 3 6 973 400B_8020 Channel n Value FTM2_C2V 32 R W 0000_0000h 41 3 7 976 400B_8024 Channel n Status and Control FTM2_C3SC 32 R W 0000_0000h...

Страница 969: ...92 400B_806C FTM External Trigger FTM2_EXTTRIG 32 R W 0000_0000h 41 3 16 993 400B_8070 Channels Polarity FTM2_POL 32 R W 0000_0000h 41 3 17 995 400B_8074 Fault Mode Status FTM2_FMS 32 R W 0000_0000h 4...

Страница 970: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FTMx_SC field descriptions Field Description 31 8 Reserved This read only field is reserved and always has the value zero 7 TOF Timer Overflow Flag Set by hardware...

Страница 971: ...01 System clock 10 Fixed frequency clock 11 External clock 2 0 PS Prescale Factor Selection Selects one of 8 division factors for the clock source selected by CLKS The new prescaler factor affects the...

Страница 972: ...e value into a buffer The MOD register is updated with the value of its write buffer according to Registers Updated from Write Buffers If FTMEN 0 this write coherency mechanism may be manually reset b...

Страница 973: ...nd control bits used to configure the interrupt enable channel configuration and pin function Table 41 67 Mode Edge and Level Selection DECAPEN COMBINE CPWMS MSnB MSnA ELSnB ELSnA Mode Configuration X...

Страница 974: ...lear Output on match X1 Low true pulses set Output on match 1 XX 10 Center aligned PWM High true pulses clear Output on match up X1 Low true pulses set Output on match up 1 0 XX 10 Combine PWM High tr...

Страница 975: ...the channel CHF is cleared by reading the CSC register while CHnF is set and then writing a 0 to the CHF bit Writing a 1 to CHF has no effect If another event occurs between the read and write operat...

Страница 976: ...nables DMA transfers for the channel 0 Disable DMA transfers 1 Enable DMA transfers 41 3 7 Channel n Value FTMx_CV These registers contain the captured FTM counter value for the input modes or the mat...

Страница 977: ...fore the first write to select the FTM clock write the new value to the the CNTIN register and then initialize the FTM counter write any value to the CNT register Addresses FTM0_CNTIN is 4003_8000h ba...

Страница 978: ...003_8000h base 50h offset 4003_8050h FTM1_STATUS is 4003_9000h base 50h offset 4003_9050h FTM2_STATUS is 400B_8000h base 50h offset 400B_8050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W...

Страница 979: ...l event has occurred 1 A channel event has occurred 2 CH2F Channel 2 Flag See the register description 0 No channel event has occurred 1 A channel event has occurred 1 CH1F Channel 1 Flag See the regi...

Страница 980: ...Description 31 8 Reserved This read only field is reserved and always has the value zero 7 FAULTIE Fault Interrupt Enable Enables the generation of an interrupt when a fault is detected by FTM and the...

Страница 981: ...N bit WPDIS is cleared when 1 is written to WPEN WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS Writing 0 to WPDIS has no effect 0 Write protection is enabled 1 Write protect...

Страница 982: ...d SYNCMODE SYNCONF register bits See PWM Synchronization Addresses FTM0_SYNC is 4003_8000h base 58h offset 4003_8058h FTM1_SYNC is 4003_9000h base 58h offset 4003_9058h FTM2_SYNC is 400B_8000h base 58...

Страница 983: ...ing edges of the system clock 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization 2 REINIT FTM Counter Reinitialization by Synchronization FTM Counter Synchroniz...

Страница 984: ...Value Selects the value that is forced into the channel output when the initialization occurs 0 The initialization value is 0 1 The initialization value is 1 6 CH6OI Channel 6 Output Initialization Va...

Страница 985: ...alue is 1 41 3 13 Output Mask FTMx_OUTMASK This register provides a mask for each FTM channel The mask of a channel determines if its output responds that is it is masked or not when a match occurs Th...

Страница 986: ...channel output is masked forced to its inactive state or unmasked it continues to operate normally 0 Channel output is not masked It continues to operate normally 1 Channel output is masked It is forc...

Страница 987: ...64h offset 400B_8064h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FAULTEN3 SYNCEN3 DTEN3 DECAP3 DECAPEN3 COMP3 COMBINE3 0 FAULTEN2 SYNCEN2 DTEN2 DECAP2 DECAPEN2 COMP2 COMBINE2 W Reset 0 0...

Страница 988: ...APEN3 Dual Edge Capture Mode Enable for n 6 Enables the dual edge capture mode in the channels n and n 1 This bit reconfigures the function of MSnA ELSnB ELSnA and ELS n 1 B ELS n 1 A bits in dual edg...

Страница 989: ...g to the channel n input event and the configuration of the dual edge capture bits This field applies only when FTMEN 1 and DECAPEN 1 DECAP bit is cleared automatically by hardware if dual edge captur...

Страница 990: ...e for n 2 Enables the deadtime insertion in the channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 The deadtime insertion in this pair of channels is disabled...

Страница 991: ...WPDIS 1 0 The fault control in this pair of channels is disabled 1 The fault control in this pair of channels is enabled 5 SYNCEN0 Synchronization Enable for n 0 Enables PWM synchronization of regist...

Страница 992: ...of the channel n output 0 COMBINE0 Combine Channels for n 0 Enables the combine feature for channels n and n 1 This field is write protected It can be written only when MODE WPDIS 1 0 Channels n and...

Страница 993: ...the number of deadtime counts inserted as follows When DTVAL is 0 no counts are inserted When DTVAL is 1 1 count is inserted When DTVAL is 2 2 counts are inserted This pattern continues up to a possi...

Страница 994: ...IGF remains set after the clear sequence is completed for the earlier TRIGF 0 No channel trigger was generated 1 A channel trigger was generated 6 INITTRIGEN Initialization Trigger Enable Enables the...

Страница 995: ...ion of the channel trigger when the FTM counter is equal to the CnV register 0 The generation of the channel trigger is disabled 1 The generation of the channel trigger is enabled 41 3 17 Channels Pol...

Страница 996: ...POL4 Channel 4 Polarity Defines the polarity of the channel output This field is write protected It can be written only when MODE WPDIS 1 0 The channel polarity is active high 1 The channel polarity i...

Страница 997: ...abled fault inputs Addresses FTM0_FMS is 4003_8000h base 74h offset 4003_8074h FTM1_FMS is 4003_9000h base 74h offset 4003_9074h FTM2_FMS is 400B_8000h base 74h offset 400B_8074h Bit 31 30 29 28 27 26...

Страница 998: ...FAULTF3 Fault Detection Flag 3 Set by hardware when fault control is enabled the corresponding fault input is enabled and a fault condition is detected at the fault input Clear FAULTF3 by reading the...

Страница 999: ...when fault control is enabled the corresponding fault input is enabled and a fault condition is detected at the fault input Clear FAULTF0 by reading the FMS register while FAULTF0 is set and then wri...

Страница 1000: ...eld is reserved 15 12 CH3FVAL Channel 3 Input Filter Selects the filter value for the channel input The filter is disabled when the value is zero 11 8 CH2FVAL Channel 2 Input Filter Selects the filter...

Страница 1001: ...he value zero 11 8 FFVAL Fault Input Filter Selects the filter value for the fault inputs The fault filter is disabled when the value is zero NOTE Writing to this field has immediate effect and must b...

Страница 1002: ...write protected It can be written only when MODE WPDIS 1 0 Fault input is disabled 1 Fault input is enabled 2 FAULT2EN Fault Input 2 Enable Enables the fault input This field is write protected It ca...

Страница 1003: ...the value zero 7 PHAFLTREN Phase A Input Filter Enable Enables the filter for the quadrature decoder phase A input The filter value for the phase A input is defined by the CH0FVAL field of FILTER The...

Страница 1004: ...ounting direction is decreasing FTM counter decrement 1 Counting direction is increasing FTM counter increment 1 TOFDIR Timer Overflow Direction in Quadrature Decoder Mode Indicates if the TOF bit was...

Страница 1005: ...Description 31 11 Reserved This read only field is reserved and always has the value zero 10 GTBEOUT Global time base output Enables the global time base signal generation to other FTMs 0 A global ti...

Страница 1006: ...FTM1_FLTPOL is 4003_9000h base 88h offset 4003_9088h FTM2_FLTPOL is 400B_8000h base 88h offset 400B_8088h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1007: ...eld is write protected It can be written only when MODE WPDIS 1 0 The fault input polarity is active high A one at the fault input indicates a fault 1 The fault input polarity is active low A zero at...

Страница 1008: ...Software output control synchronization is activated by a hardware trigger 0 A hardware trigger does not activate the SWOCTRL register synchronization 1 A hardware trigger activates the SWOCTRL regist...

Страница 1009: ...ed by the software trigger 0 The software trigger does not activate MOD CNTIN and CV registers synchronization 1 The software trigger activates MOD CNTIN and CV registers synchronization 8 SWRSTCNT FT...

Страница 1010: ...ister has a write buffer The INVmEN bit is updated by the INVCTRL register synchronization Addresses FTM0_INVCTRL is 4003_8000h base 90h offset 4003_8090h FTM1_INVCTRL is 4003_9000h base 90h offset 40...

Страница 1011: ...re updated by the SWOCTRL register synchronization Addresses FTM0_SWOCTRL is 4003_8000h base 94h offset 4003_8094h FTM1_SWOCTRL is 4003_9000h base 94h offset 4003_9094h FTM2_SWOCTRL is 400B_8000h base...

Страница 1012: ...software output control forces 0 to the channel output 1 The software output control forces 1 to the channel output 9 CH1OCV Channel 1 Software Output Control Value 0 The software output control forc...

Страница 1013: ...e 0 The channel output is not affected by software output control 1 The channel output is affected by software output control 41 3 27 FTM PWM Load FTMx_PWMLOAD Enables the loading of the MOD CNTIN C n...

Страница 1014: ...el 5 Select 0 Do not include the channel in the matching process 1 Include the channel in the matching process 4 CH4SEL Channel 4 Select 0 Do not include the channel in the matching process 1 Include...

Страница 1015: ...high true EPWM mode PS 2 0 001 CNTIN 0x0000 MOD 0x0004 CnV 0x0002 Figure 41 166 Notation Used 41 4 1 Clock Source FTM module has only one clock domain that is the system clock 41 4 1 1 Counter Clock...

Страница 1016: ...system clock frequency 41 4 2 Prescaler The selected counter clock source passes through a prescaler that is a 7 bit counter The value of the prescaler is selected by the PS 2 0 bits The following fig...

Страница 1017: ...ounter clock MOD 0x0004 TOF bit set TOF bit set TOF bit set TOF bit 4 4 3 2 1 4 3 2 1 0 1 2 3 4 0 1 2 3 4 4 3 CNTIN 0xFFFC in two s complement is equal to 4 period of counting MOD CNTIN 0x0001 x perio...

Страница 1018: ...his requirement Any values of CNTIN and MOD that do not satisfy this criteria can result in unpredictable behavior MOD CNTIN is a redundant condition In this case the FTM counter is always equal to MO...

Страница 1019: ...final value of the count The value of CNTIN is loaded into the FTM counter and the counter increments until the value of MOD is reached at which point the counter is decremented until it returns to t...

Страница 1020: ...counter In this case the FTM counter runs free from 0x0000 through 0xFFFF and the TOF bit is set when the FTM counter changes from 0xFFFF to 0x0000 see the following figure FTM counter 0x0004 0x0004...

Страница 1021: ...0 bits define the number of times that the FTM counter overflow should occur before the TOF bit to be set If NUMTOF 4 0 0x00 then the TOF bit is set at each FTM counter overflow FTM counter NUMTOF 4...

Страница 1022: ...ptured into the CnV register and the CHnF bit is set channel n input synchronizer 1 is filter enabled edge detector was falling edge selected was rising edge selected rising edge falling edge 0 1 1 0...

Страница 1023: ...in Any pulse that is shorter than the minimum value selected by CHnFVAL 3 0 bits 4 system clocks is regarded as a glitch and is not passed on to the edge detector A timing diagram of the input filter...

Страница 1024: ...rrupt is generated if CHnIE 1 at the channel n match FTM counter CnV TOF bit 0 1 1 1 2 2 3 3 4 4 5 5 0 0 previous value previous value channel n output counter overflow counter overflow counter overfl...

Страница 1025: ...Aligned PWM EPWM Mode The edge aligned mode is selected when QUADEN 0 DECAPEN 0 COMBINE 0 CPWMS 0 and MSnB 1 The EPWM period is determined by MOD CNTIN 0x0001 and the pulse width duty cycle is determi...

Страница 1026: ...at the counter overflow when the CNTIN register value is loaded into the FTM counter and it is forced high at the channel n match FTM counter CnV see the following figure TOF bit CHnF bit CNT channel...

Страница 1027: ...channels are aligned with the value of CNTIN The other channel modes are not compatible with the up down counter CPWMS 1 Therefore all FTM channels must be used in CPWM mode when CPWMS 1 pulse width...

Страница 1028: ...0x0005 Figure 41 186 CPWM Signal with ELSnB ELSnA X 1 If CnV 0x0000 or CnV is a negative value that is CnV 15 1 then the channel n output is a 0 duty cycle CPWM signal and CHnF bit is not set even wh...

Страница 1029: ...match FTM counter C n 1 V It is forced high at the channel n match FTM counter C n V see the following figure If ELSnB ELSnA X 1 then the channel n output is forced high at the beginning of the period...

Страница 1030: ...with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 MOD C n 1 V C n V CNTIN Figure 41 189 Channel n Output If CNTIN C n V MOD and C n 1 V MOD FTM counter C n 1 V channel n output with ELSnB ELS...

Страница 1031: ...C n V is Almost Equal to CNTIN and C n 1 V MOD FTM counter not fully 100 duty cycle channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 not fully 0 duty cycle MOD C n V CNTIN C...

Страница 1032: ...V and C n 1 V Are Not Between CNTIN and MOD FTM counter 0 duty cycle channel n output with ELSnB ELSnA 1 0 channel n output with ELSnB ELSnA X 1 100 duty cycle MOD CNTIN C n 1 V C n V Figure 41 194 C...

Страница 1033: ...SnB ELSnA X 1 100 duty cycle 0 duty cycle MOD C n 1 V C n V Figure 41 196 Channel n Output If C n V C n 1 V MOD channel n match is ignored FTM counter channel n output with ELSnB ELSnA 1 0 channel n o...

Страница 1034: ...e 41 198 Channel n Output If C n V CNTIN and CNTIN C n 1 V MOD C n 1 V channel n output with ELSnB ELSnA X 1 FTM counter CNTIN channel n output with ELSnB ELSnA 1 0 C n V MOD Figure 41 199 Channel n O...

Страница 1035: ...re 41 200 Channel n Output If C n V MOD and CNTIN C n 1 V MOD C n V CNTIN channel n output with ELSnB ELSnA X 1 channel n output with ELSnB ELSnA 1 0 FTM counter C n 1 V MOD Figure 41 201 Channel n Ou...

Страница 1036: ...rol of the PWM signal second edge when the channel n 1 match occurs that is FTM counter C n 1 V So combine mode allows the generation of asymmetrical PWM signals 41 4 9 Complementary Mode The compleme...

Страница 1037: ...10 Registers Updated from Write Buffers 41 4 10 1 CNTIN Register Update If CLKS 1 0 0 0 then CNTIN register is updated when CNTIN register is written independent of FTMEN bit If FTMEN 0 or CNTINC 0 t...

Страница 1038: ...register is written independent of FTMEN bit If CLKS 1 0 0 0 and FTMEN 0 then CnV register is updated according to the selected mode that is If the selected mode is output compare then CnV register i...

Страница 1039: ...ion SYNCMODE 0 is a subset of the enhanced PWM synchronization SYNCMODE 1 Thus it is expected that only the enhanced PWM synchronization be used 41 4 11 1 Hardware Trigger Three hardware trigger signa...

Страница 1040: ...lso initiated by the software trigger event then this new synchronization is started and SWSYNC bit remains equal to 1 If SYNCMODE 0 then the SWSYNC bit is also cleared by FTM according to PWMSYNC and...

Страница 1041: ...ounter turns from down to up counting and when from up to down counting The following figure shows the boundary cycles and the loading points In the up counting mode the loading points are enabled if...

Страница 1042: ...ue This synchronization is enabled if FTMEN 1 The MOD register synchronization can be done by either the enhanced PWM synchronization SYNCMODE 1 or the legacy PWM synchronization SYNCMODE 0 However it...

Страница 1043: ...bit wait hardware trigger n HWTRIGMODE bit clear TRIGn bit wait the next selected loading point update MOD with its buffer value update MOD with its buffer value HWRSTCNT bit Figure 41 208 MOD Registe...

Страница 1044: ...r is updated write 1 to TRIG0 bit TRIG0 bit trigger 0 event Figure 41 210 MOD Synchronization with SYNCMODE 0 HWTRIGMODE 0 PWMSYNC 0 REINIT 0 and a Hardware Trigger Was Used If SYNCMODE 0 PWMSYNC 0 an...

Страница 1045: ...PWMSYNC 0 REINIT 1 and a Hardware Trigger Was Used If SYNCMODE 0 and PWMSYNC 1 then this synchronization is made on the next selected loading point after the software trigger event takes place The SWS...

Страница 1046: ...is the same as the MOD register synchronization MOD Register Synchronization However it is expected that the C n V and C n 1 V registers be synchronized only by the enhanced PWM synchronization SYNCM...

Страница 1047: ...trigger n TRIGn bit HWOM bit SWOM bit SWSYNC bit rising edge of system clock update OUTMASK with its buffer value hardware trigger OUTMASK is updated by software trigger OUTMASK is updated by hardwar...

Страница 1048: ...SWSYNC bit software trigger event Figure 41 215 OUTMASK Synchronization with SYNCMODE 0 SYNCHOM 1 PWMSYNC 0 and Software Trigger Was Used system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OU...

Страница 1049: ...NVCTRL register synchronization updates the INVCTRL register with its buffer value The INVCTRL register can be updated at each rising edge of system clock INVC 0 or by the enhanced PWM synchronization...

Страница 1050: ...bit rising edge of system clock update INVCTRL with its buffer value update INVCTRL with its buffer value HWINVC bit TRIGn bit wait hardware trigger n update INVCTRL with its buffer value HWTRIGMODE b...

Страница 1051: ...SWOCTRL is updated by hardware trigger enhanced PWM synchronization update SWOCTRL register by PWM synchronization update SWOCTRL register at each rising edge of system clock yes 0 1 0 0 no 1 SWOC bit...

Страница 1052: ...t from transitioning to 1 If no deadtime insertion is selected then the channel n 1 transitions to logical value 1 immediately after the synchronization event had occurred synchronization event channe...

Страница 1053: ...ware trigger TRIGn bit 0 0 0 0 0 1 Figure 41 221 FTM Counter Synchronization Flowchart In the case of legacy PWM synchronization the FTM counter synchronization depends on REINIT and PWMSYNC bits acco...

Страница 1054: ...FTM Counter Synchronization with SYNCMODE 0 HWTRIGMODE 0 REINIT 1 PWMSYNC 0 and a Hardware Trigger Was Used If SYNCMODE 0 REINIT 1 and PWMSYNC 1 then this synchronization is made on the next enabled...

Страница 1055: ...NOTE channel n 1 match FTM counter channel n match channel n 1 output before the inverting write 1 to INV m bit INV m bit buffer INVCTRL register synchronization INV m bit channel n output after the i...

Страница 1056: ...forces the channel output according to software defined values at a specific time in the PWM generation The software output control is selected when FTMEN 1 QUADEN 0 DECAPEN 0 COMBINE 1 CPWMS 0 and CH...

Страница 1057: ...OCV Channel n Output Channel n 1 Output 0 0 X X is not modified by SWOC is not modified by SWOC 1 1 0 0 is forced to zero is forced to zero 1 1 0 1 is forced to zero is forced to one 1 1 1 0 is force...

Страница 1058: ...s channels n and n 1 drive the active state at the same time If POL n 0 POL n 1 0 and the deadtime is enabled then when the channel n match FTM counter C n V occurs the channel n output remains at the...

Страница 1059: ...t before deadtime insertion channel n 1 output before deadtime insertion channel n output after deadtime insertion channel n 1 output after deadtime insertion channel n match Figure 41 229 Deadtime In...

Страница 1060: ...annel n output before deadtime insertion channel n output after deadtime insertion channel n 1 output before deadtime insertion channel n 1 output after deadtime insertion Figure 41 230 Example of the...

Страница 1061: ...following figure FTM counter channel n output before output mask CHnOM bit channel n output after output mask the beginning of new PWM cycles configured PWM signal starts to be available in the chann...

Страница 1062: ...fault input n value is validated It is then transmitted as a pulse edge to the edge detector If the opposite edge appears on the fault input n signal before validation counter overflow the counter is...

Страница 1063: ...0 FAULTF1 FAULTF2 FAULTF3 Figure 41 234 FAULTF and FAULTIN Bits and Fault Interrupt If the fault control is enabled FAULTM 1 0 0 0 a fault condition has occurred rising edge at the logic OR of the ena...

Страница 1064: ...clearing and POLn 0 the beginning of new PWM cycles FAULTF bit FAULTF bit is cleared The channel n output is after the fault control with automatic fault clearing and POLn 0 NOTE Figure 41 235 Fault C...

Страница 1065: ...3 If FLTjPOL 0 the fault j input polarity is high so the logical one at the fault input j indicates a fault If FLTjPOL 1 the fault j input polarity is low so the logical zero at the fault input j indi...

Страница 1066: ...one is forced to zero 1 1 is forced to one is forced to one The following table shows the values that channels n and n 1 are forced by initialization when COMP 1 or DTEN 1 Table 41 246 Initialization...

Страница 1067: ...I COMP m INV m EN CH n OC CH n OCV CH n 1 OC CH n 1 OCV DTEN m CH n OM CH n 1 OM FAULTEN m POL n POL n 1 Figure 41 237 Priority of the Features Used at the Generation of Channels n and n 1 Outputs Sig...

Страница 1068: ...TRIG 1 CH4TRIG 1 CH5TRIG 1 the beginning of new PWM cycles MOD FTM counter C5V FTM counter C4V FTM counter C3V FTM counter C2V FTM counter C1V FTM counter C0V CNTIN a b c d Figure 41 238 Channel Match...

Страница 1069: ...nting Achieves the CNTIN Register Value CPWMS 0 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 initialization trigger write to CNT FTM counter system clock CNTIN 0x0000 MOD 0x000F Figure 41 240 Ini...

Страница 1070: ...ode all channels must be configured for input capture mode Input Capture Mode and FTM counter must be configured to the up counting Up Counting When the capture test mode is enabled CAPTEST 1 the FTM...

Страница 1071: ...ransfer Request DMA CHnIE Channel DMA Transfer Request Channel Interrupt 0 0 The channel DMA transfer request is not generated The channel interrupt is not generated 0 1 The channel DMA transfer reque...

Страница 1072: ...CAPEN DECAP MS n A ELS n B ELS n A ELS n 1 B ELS n 1 A CLK CLK D Q D Q 0 1 Figure 41 244 Dual Edge Capture Mode Block Diagram The MS n A bit defines if the dual edge capture mode is one shot or contin...

Страница 1073: ...apture mode is selected when FTMEN 1 DECAPEN 1 and MS n A 0 In this capture mode only one pair of edges at the channel n input is captured The ELS n B ELS n A bits select the first edge to be captured...

Страница 1074: ...hannel n is configured to capture rising edges ELS n B ELS n A 0 1 and the channel n 1 to capture falling edges ELS n 1 B ELS n 1 A 1 0 then the positive polarity pulse width is measured If the channe...

Страница 1075: ...Polarity Pulse Width Measurement The following figure shows an example of the dual edge capture continuous mode used to measure the positive polarity pulse width The DECAPEN bit selects the dual edge...

Страница 1076: ...and n 1 are configured to capture consecutive edges of the same polarity then the period of the channel n input signal is measured If both channels n and n 1 are configured to capture rising edges EL...

Страница 1077: ...5 Note The commands set DECAPEN set DECAP clear CH n F and clear CH n 1 F are made by the user 4 9 11 12 13 14 6 15 16 17 18 19 20 21 22 23 24 25 26 27 28 17 20 15 20 23 C n V CH n 1 F bit CH n F bit...

Страница 1078: ...11 19 21 23 25 27 23 20 19 17 7 9 11 13 15 6 8 10 12 16 14 24 22 20 18 26 25 21 Figure 41 248 Dual Edge Capture Continuous Mode to Measure of the Period Between Two Consecutive Rising Edges 41 4 24 5...

Страница 1079: ...register in dual edge capture one shot and continuous modes for the read coherency mechanism works properly read C n 1 V FTM counter channel n input after the filter channel input channel n capture bu...

Страница 1080: ...notice that the FTM counter is clocked by the phase A and B input signals when quadrature decoder mode is selected Therefore it is expected that the quadrature decoder be used only with the FTM chann...

Страница 1081: ...ment happens when there is a rising edge at phase A signal and phase B signal is at logic zero there is a rising edge at phase B signal and phase A signal is at logic one there is a falling edge at ph...

Страница 1082: ...TM counter overflow occurred phase A phase B FTM counter increment decrement FTM counter MOD CNTIN 0x0000 Time 1 1 1 1 1 1 1 set TOF set TOFDIR set TOF set TOFDIR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Fig...

Страница 1083: ...1 Quadrature Decoder Boundary Conditions The following figures are examples of motor jittering which causes the FTM counter transitions as indicated by these figures It is expected to observe these be...

Страница 1084: ...oscillations that can be caused by poor input filter setup Thus it is important to guarantee a minimum pulse width to avoid these oscillations 41 4 26 BDM Mode When the chip is in BDM mode the BDMODE...

Страница 1085: ...TIN register value and the channels outputs are updated to the initial value except for channels in output compare mode In the channels outputs initialization Initialization the channel n output is fo...

Страница 1086: ...hannels n and n 1 then the C n 1 V register is updates with its write buffer value NOTE c a LDOK 0 CH0SEL 0 CH1SEL 0 CH2SEL 0 CH3SEL 0 CH4SEL 0 CH5SEL 0 CH6SEL 0 CH7SEL 0 b LDOK 1 CH0SEL 0 CH1SEL 0 CH...

Страница 1087: ...e following figure shows an example of the GTB feature used to synchronize two FTM modules In this case the FTM A and B channels can behave as if just one FTM module was used that is a global time bas...

Страница 1088: ...ows the FTM counters to start their operation synchronously 41 4 28 1 Enabling the global time base GTB To enable the GTB feature follow these steps for each participating FTM module 1 Stop the FTM co...

Страница 1089: ...e the channels mode and CnV registers value according to the channels mode Thus it is recommended to write any value to CNT register item 3 This write updates the FTM counter with the CNTIN register v...

Страница 1090: ...n output 5 write 1 to SC CLKS 3 write any value to CNT register 2 FTM configuration channel n pin is controlled by FTM NOTES CNTIN 0x0010 Channel n is in output compare and the channel n output is tog...

Страница 1091: ...41 6 3 Fault Interrupt The fault interrupt is generated when FAULTIE 1 and FAULTF 1 Chapter 41 FlexTimer FTM K53 Sub Family Reference Manual Rev 6 Nov 2011 Freescale Semiconductor Inc 1091...

Страница 1092: ...FTM Interrupts K53 Sub Family Reference Manual Rev 6 Nov 2011 1092 Freescale Semiconductor Inc...

Страница 1093: ...his module s instances see the chip configuration chapter The PIT timer module is an array of timers that can be used to raise interrupts and trigger DMA channels 42 1 1 Block Diagram The following fi...

Страница 1094: ...he number of PIT channels used in this MCU 42 1 2 Features The main features of this block are Timers can generate DMA trigger pulses Timers can generate interrupts All interrupts are maskable Indepen...

Страница 1095: ...TRL0 32 R W 0000_0000h 42 3 4 1098 4003_710C Timer Flag Register PIT_TFLG0 32 R W 0000_0000h 42 3 5 1098 4003_7110 Timer Load Value Register PIT_LDVAL1 32 R W 0000_0000h 42 3 2 1097 4003_7114 Current...

Страница 1096: ...03_7000h base 0h offset 4003_7000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MDIS FRZ W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1097: ...pires To abort the current cycle and start a timer period with the new value the timer must be disabled and enabled again 42 3 3 Current Timer Value Register PIT_CVALn These registers indicate the cur...

Страница 1098: ...interrupt will immediately cause an interrupt event To avoid this the associated TIF flag must be cleared first 0 Interrupt requests from Timer n are disabled 1 Interrupt will be requested whenever T...

Страница 1099: ...terrupt is available on a separate interrupt line 42 4 1 1 Timers The timers generate triggers at periodic intervals when enabled They load their start values as specified in their LDVAL registers the...

Страница 1100: ...ut restarting the timer by writing the LDVAL register with the new load value This value will then be loaded after the next trigger event see the following figure Timer Enabled p1 p1 Start Value p1 Tr...

Страница 1101: ...trigger every 5 12 ms 20 ns 256000 cycles and timer 3 every 30 ms 20 ns 1500000 cycles The value for the LDVAL register trigger is calculated as LDVAL trigger period clock period 1 This means LDVAL1...

Страница 1102: ..._LDVAL3 0x0016E35F setup timer 3for 1500000 cycles PIT_TCTRL3 TEN start Timer 3 Initialization and Application Information K53 Sub Family Reference Manual Rev 6 Nov 2011 1102 Freescale Semiconductor I...

Страница 1103: ...tem reset events allowing it to be used as a time of day counter 43 1 1 Features The LPTMR module s features include 16 bit time counter or pulse counter with compare Optional interrupt can generate a...

Страница 1104: ...rrupt request 43 1 2 4 Low leakage modes In low leakage modes the LPTMR continues to operate normally and may be configured to exit the low power mode by generating an interrupt request 43 1 2 5 Debug...

Страница 1105: ...input may assert asynchronously to the bus clock 43 3 Memory map and register definition NOTE The LPTMR registers are reset only on a POR or LVD event See LPTMR power and reset for more details LPTMR...

Страница 1106: ...has not equaled the LPTMR Compare Register and incremented 1 LPTMR Counter Register has equaled the LPTMR Compare Register and incremented 6 TIE Timer Interrupt Enable When the Timer Interrupt Enable...

Страница 1107: ...S Timer Mode Select The Timer Mode Select configures the mode of the LPTMR The Timer Mode Select should only be altered when the LPTMR is disabled 0 Time Counter mode 1 Pulse Counter mode 0 TEN Timer...

Страница 1108: ...es 1010 Prescaler divides the prescaler clock by 2048 Glitch Filter recognizes change on input pin after 1024 rising clock edges 1011 Prescaler divides the prescaler clock by 4096 Glitch Filter recogn...

Страница 1109: ...ue in the LPTMR Compare Register and increments the Timer Compare Flag is set and the Hardware Trigger asserts until the next time the LPTMR Counter Register increments If the LPTMR Compare Register i...

Страница 1110: ...nsures the LPTMR is configured correctly and the LPTMR counter is reset to zero following a warm reset 43 4 2 LPTMR clocking The LPTMR prescaler glitch filter can be clocked by one of four clocks The...

Страница 1111: ...clock cycles due to synchronization logic 43 4 3 3 Glitch filter In pulse counter mode when the glitch filter is enabled the output of the glitch filter directly clocks the LPTMR counter register Whe...

Страница 1112: ...r can only be altered when the timer compare flag is set When updating the LPTMR compare register the LPTMR compare register must be written and the timer compare flag must be cleared before the LPTMR...

Страница 1113: ...e running counter bit clear the LPTMR hardware trigger will assert on the first compare and does not negate When the LPTMR compare register is set to a non zero value or if the free running counter bi...

Страница 1114: ...Functional description K53 Sub Family Reference Manual Rev 6 Nov 2011 1114 Freescale Semiconductor Inc...

Страница 1115: ...d scanning The CMT does not include dedicated hardware configurations for specific protocols but is intended to be sufficiently programmable in its function to handle the timing requirements of most p...

Страница 1116: ...use as timer interrupt 44 3 Block Diagram The following figure is the CMT block diagram Modulator CMT_IRO Carrier Generator CMT Registers Clock Divider CMT Interrupts Peripheral bus clock Peripheral b...

Страница 1117: ...2 MSC FSK 2 MSC EXSPC Comment Time 1 0 0 0 fcg controlled by primary high and low registers fcg transmitted to CMT_IRO signal when modulator gate is open Baseband 1 1 X 0 fcg is always high CMT_IRO s...

Страница 1118: ...ld ensure that the Normal Stop mode is not entered while the modulator is still in operation to prevent the CMT_IRO signal from being asserted while in Normal Stop mode This may require a time out per...

Страница 1119: ...software to directly control the state of the CMT_IRO signal by writing to OC IROL bit If OC IROPEN bit is cleared the signal is disabled and is not driven by the CMT module Therefore CMT can be conf...

Страница 1120: ...er Mark High CMT_CMD1 8 R W Undefined 44 6 7 1125 4006_2007 CMT Modulator Data Register Mark Low CMT_CMD2 8 R W Undefined 44 6 8 1126 4006_2008 CMT Modulator Data Register Space High CMT_CMD3 8 R W Un...

Страница 1121: ...value for generating the carrier output Address CMT_CGL1 is 4006_2000h base 1h offset 4006_2001h Bit 7 6 5 4 3 2 1 0 Read PL Write Reset x x x x x x x x Notes x Undefined at reset CMT_CGL1 field descr...

Страница 1122: ...enerator is enabled when operating in FSK mode 44 6 4 CMT Carrier Generator Low Data Register 2 CMT_CGL2 This data register contain the secondary low value for generating the carrier output Address CM...

Страница 1123: ...low 1 CMT_IRO signal is active high 5 IROPEN IRO Pin Enable The IROPEN bit is used to enable and disable the CMT_IRO signal When CMT_IRO signal is enabled it is an output that drives out either the C...

Страница 1124: ...ter At this time the counter is initialized with the possibly new contents of the mark period buffer CMT_CMD1 and CMT_CMD2 and the space period register is loaded with the possibly new contents of the...

Страница 1125: ...nd Carrier Generator Enable Setting MCGEN will initialize the carrier generator and modulator and will enable all clocks Once enabled the carrier generator and modulator will function continuously Whe...

Страница 1126: ...x x x x x x x x Notes x Undefined at reset CMT_CMD2 field descriptions Field Description 7 0 MB 7 0 These bits control the lower mark periods of the modulator for all modes 44 6 9 CMT Modulator Data...

Страница 1127: ...d descriptions Field Description 7 0 SB 7 0 These bits control the lower space periods of the modulator for all modes 44 6 11 CMT Primary Prescaler Register CMT_PPS This register is used to set the pr...

Страница 1128: ...ck 13 1101 Bus Clock 14 1110 Bus Clock 15 1111 Bus Clock 16 44 6 12 CMT Direct Memory Access CMT_DMA This register is used to enable disable direct memory access DMA Address CMT_DMA is 4006_2000h base...

Страница 1129: ...agram Primary Prescaler if_clk_enable divider_enable Bus clock Secondary Prescaler Figure 44 14 Clock Divider Block Diagram For compatibility with previous versions of CMT when bus clock 8 MHz the PPS...

Страница 1130: ...number of input clocks 125 ns for an 8 MHz bus for both the carrier high time and the carrier low time The period is determined by the total number of clocks counted The duty cycle is determined by th...

Страница 1131: ...re register is currently active a valid compare will cause the carrier output to be driven low The counter will continue to increment starting at reset value of 0x01 When the value stored in the selec...

Страница 1132: ...pires The modulator provides a simple method to control protocol timing The modulator has a minimum resolution of 1 0 s with an 8 MHz It can count bus clocks to provide real time control or it can cou...

Страница 1133: ...C O N D A R Y S E LE C T 0 16 17 BIT DOWN COUNTER CMTCMD1 CMTCMD2 CLOCK CONTROL CARRIER OUT fcg MODULATOR OUT MODULATOR GATE EOC FLAG SET MODULE INTERRUPT REQUEST SYSTEM CONTROL CMTCLOCK SPACE PERIOD...

Страница 1134: ...n CMTCLK 8 counts The mark and space calculations are the same as in time mode In this mode the modulator output will be at a logic 1 for the duration of the mark period and at a logic 0 for the durat...

Страница 1135: ...0x0000 then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glitches zero space Using timing data for carrier burst and interpulse gap length...

Страница 1136: ...equent modulation periods will consist entirely of these extended space periods with no mark periods Clearing MSC EXSPC will return the modulator to standard operation at the beginning of the next mod...

Страница 1137: ...space period ends at the completion of the space period time of the modulation period during which MSC EXSPC bit is cleared If MSC EXSPC bit was set during a primary modulation cycle use the equation...

Страница 1138: ...or DMA request after exiting the service routine See following table Table 44 19 How to clear MSC EOCF bit DMA DM A MSC EOCIE Description 0 X MSC EOCF bit is cleared by reading the CMT modulator stat...

Страница 1139: ...otection and 32 bit alarm 16 bit prescaler with compensation that can correct errors between 0 12 ppm and 3906 ppm Register write protection Lock register requires VBAT POR or software reset to enable...

Страница 1140: ...llator output O RTC_CLKOUT 1Hz square wave output O RTC_WAKEUP Wakeup for external device O 45 1 3 1 RTC clock output The clock to the seconds counter is available on the RTC_CLKOUT signal It is a 1Hz...

Страница 1141: ...C Time Alarm Register RTC_TAR 32 R W 0000_0000h 45 2 3 1142 4003_D00C RTC Time Compensation Register RTC_TCR 32 R W 0000_0000h 45 2 4 1143 4003_D010 RTC Control Register RTC_CR 32 R W 0000_0000h 45 2...

Страница 1142: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TPR field descriptions Field Description 31 16 Reserved This read only field is reserved and always has the value zero 15 0 TPR...

Страница 1143: ...oes not equal zero then it is loaded with zero compensation is not enabled for that second increment 15 8 CIR Compensation Interval Register Configures the compensation interval in seconds from 1 to 2...

Страница 1144: ...d only field is reserved and always has the value zero 14 Reserved This field is reserved It must always be written to 0 13 SC2P Oscillator 2pF load configure 0 Disable the load 1 Enable the additiona...

Страница 1145: ...or SR TOF are set or if the SR TCE is clear 0 Registers cannot be written when locked 1 Registers can be written when locked under limited conditions 2 SUP Supervisor Access 0 Non supervisor mode wri...

Страница 1146: ...TAF Time Alarm Flag Time alarm flag is set when the TAR TAR equals the TSR TSR and the TSR TSR increments This bit is cleared by writing the TAR register 0 Time alarm has not occurred 1 Time alarm ha...

Страница 1147: ...writes complete as normal 5 SRL Status Register Lock Once cleared this bit can only be set by VBAT POR or software reset 0 Status register is locked and writes are ignored 1 Status register is not loc...

Страница 1148: ...s has the value zero 7 5 Reserved This field is reserved 4 Reserved This field is reserved 3 Reserved This field is reserved 2 TAIE Time Alarm Interrupt Enable 0 Time alarm flag does not generate an i...

Страница 1149: ...rmal 5 SRW Status Register Write Once cleared this bit is only set by system reset It is not affected by VBAT POR or software reset 0 Writes to the status register are ignored 1 Writes to the status r...

Страница 1150: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RTC_RAR field descriptions Field Description 31 8 Reserved This read only field is reserved and always has the value zero 7 IERR Interrupt Enable...

Страница 1151: ...tem reset It is not affected by VBAT POR or software reset 0 Reads to the time prescaler register are ignored 1 Reads to the time prescaler register complete as normal 0 TSRR Time Seconds Register Rea...

Страница 1152: ...tal oscillator includes tunable capacitors that can be configured by software Do not change the capacitance unless the oscillator is disabled 45 3 1 2 Software reset Writing one to the CR SWR forces t...

Страница 1153: ...n correct errors as high as 3906 ppm and as low as 0 12 ppm Note that the compensation factor must be calculated externally to the RTC and supplied by software to the compensation register The RTC its...

Страница 1154: ...ill prevent the time alarm flag from setting again The time alarm flag cannot otherwise be disabled although the interrupt it generates is enabled or disabled by IER TAIE 45 3 5 Update mode The update...

Страница 1155: ...is powered down The RTC interrupt is enabled at the chip level by enabling the chip specific RTC clock gate control bit The RTC Interrupt can be used to wakeup the chip from any low power mode The opt...

Страница 1156: ...Functional description K53 Sub Family Reference Manual Rev 6 Nov 2011 1156 Freescale Semiconductor Inc...

Страница 1157: ...10 100Mbps Ethernet LANs The MAC operation is fully programmable and can be used in NIC Network Interface Card bridging or switching applications The core implements the remote network monitoring RMON...

Страница 1158: ...Reduced MII RMII operating at 50 MHz Simple 64 Bit FIFO interface to user application CRC 32 checking at full speed with optional forwarding of the frame check sequence FCS field to the client CRC 32...

Страница 1159: ...management with two programmable MDIO base addresses Supports legacy FEC buffer descriptors 46 1 2 2 IP Protocol Performance Optimization Features Operates on TCP IP and UDP IP and ICMP IP protocol d...

Страница 1160: ...46 1 2 3 IEEE 1588 Features Support for all IEEE 1588 frames Reference clock can be chosen independently of the network speed Software programmable precise time stamping of ingress and egress frames...

Страница 1161: ...0 Ethernet MAC NET Core Block Diagram 46 2 External Signal Description MII RMII Description I O MII_COL Asserted upon detection of a collision and remains asserted while the collision persists This si...

Страница 1162: ...roller when RXDV is asserted I MII_RXER RMII_RXER When asserted with RXDV indicates the PHY detects an error in the current frame I MII_TXCLK Input clock which provides a timing reference for TXEN TXD...

Страница 1163: ...ET_1588_CLKIN ENET_1588_CLKIN Alternate IEEE 1588 Ethernet clock input I 46 3 Memory Map Register Definition Reserved bits should be written with 0 and ignored on read to allow future extension Unused...

Страница 1164: ...0h 46 3 10 1180 400C_00E4 Physical Address Lower Register ENET_PALR 32 R W 0000_0000h 46 3 11 1182 400C_00E8 Physical Address Upper Register ENET_PAUR 32 R W 0000_8808h 46 3 12 1182 400C_00EC Opcode P...

Страница 1165: ...000Ch 46 3 29 1191 400C_01B0 Frame Truncation Length ENET_FTRL 32 R W 0000_07FFh 46 3 30 1192 400C_01C0 Transmit Accelerator Function Configuration ENET_TACC 32 R W 0000_0000h 46 3 31 1192 400C_01C4 R...

Страница 1166: ...46 3 41 1200 400C_0624 Timer Compare Capture Register ENET_TCCR3 32 R W 0000_0000h 46 3 42 1201 46 3 1 Interrupt Event Register ENET_EIR When an event occurs that sets a bit in EIR an interrupt occurs...

Страница 1167: ...ed and the last corresponding buffer descriptor has been updated 24 RXB Receive Buffer Interrupt Indicates a receive buffer descriptor not the last in the frame has been updated 23 MII MII Interrupt I...

Страница 1168: ...the timer period value before setting ATCR PEREN 14 0 Reserved This read only field is reserved and always has the value zero 46 3 2 Interrupt Mask Register ENET_EIMR EIMR controls which interrupt ev...

Страница 1169: ...ponding EIR GRA bit reflects the state of the interrupt signal even if the corresponding EIMR bit is cleared 0 The corresponding interrupt source is masked 1 The corresponding interrupt source is not...

Страница 1170: ...source The corresponding EIR LC bit reflects the state of the interrupt signal even if the corresponding EIMR bit is cleared 20 RL RL interrupt mask Corresponds to interrupt source RL defined by the...

Страница 1171: ...ng the receive descriptor ring has been updated the driver produced empty receive buffers with the empty bit set When the register is written the RDAR bit is set This is independent of the data actual...

Страница 1172: ...at contains a ready bit that is not set the MAC clears TDAR and ceases transmit descriptor ring polling until the user sets the bit again signifying additional descriptors have been placed into the tr...

Страница 1173: ...STOPEN Signal Control Controls device behavior in doze mode In doze mode if this bit is set then all the clocks of the ENET assembly are disabled except the RMII MII clock Doze mode is like a conditi...

Страница 1174: ...following conditions RESET is set by software An error condition causes the EBERR bit to set 0 Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitt...

Страница 1175: ...pecified PHY device 17 16 TA Turn around This field must be programmed to 10 to generate a valid MII management frame 15 0 DATA Management frame data This is the field for data to be written to or rea...

Страница 1176: ...et 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 HOLDTIME DIS_PRE MII_SPEED 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENET_MSCR field descriptions Field Description 31...

Страница 1177: ...trol Register ENET_MIBC MIBC is a read write register controlling and observing the state of the MIB block Access this register to disable the MIB block operation or clear the MIB counters The MIB_DIS...

Страница 1178: ...ion 31 GRS Graceful receive stopped Read only status indicating that the MAC receive datapath is stopped 30 NLC Payload length check disable Enables disables a payload length check 0 The payload lengt...

Страница 1179: ...forwarded to the user application 12 PADEN Enable frame padding remove on receive Specifies whether the MAC removes padding from received frames 0 No padding is removed on receive by the MAC 1 Paddin...

Страница 1180: ...duplex mode 1 Disable reception of frames while transmitting normally used for half duplex mode 0 LOOP Internal loopback 0 Loopback disabled 1 Transmitted frames are looped back internal to the device...

Страница 1181: ...opped the MAC transmits a MAC control PAUSE frame Next the MAC clears TFC_PAUSE and resumes transmitting data frames If the transmitter pauses due to user assertion of GTS or reception of a PAUSE fram...

Страница 1182: ...Physical Address Upper Register ENET_PAUR PAUR contains the upper 16 bits bytes 4 and 5 of the 48 bit address used in the address recognition process to compare with the DA destination address field...

Страница 1183: ...0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENET_OPD field descriptions Field Description 31 16 OPCODE Opcode field in PAUSE frames These bits have a constant value of 0x0001 15 0 PAUSE_DUR...

Страница 1184: ...1 0 IADDR2 The lower 32 bits of the 64 bit hash table used in the address recognition process for receive frames with a unicast address Bit 31 of IADDR2 contains hash index bit 31 Bit 0 of IADDR2 cont...

Страница 1185: ...ermark Register ENET_TFWR If TFR STRFWD is cleared TFWR TFWR controls the amount of data required in the transmit FIFO before transmission of a frame can begin This allows you to minimize transmit lat...

Страница 1186: ...tes written 111111 4032 bytes written 46 3 19 Receive Descriptor Ring Start Register ENET_RDSR RDSR points to the start of the circular receive buffer descriptor queue in external memory This pointer...

Страница 1187: ...s has the value zero 46 3 21 Maximum Receive Buffer Size Register ENET_MRBR The MRBR is a user programmable register that dictates the maximum size of all receive buffers This value should take into c...

Страница 1188: ...7 0 RX_SECTION_ FULL Value of receive FIFO section full threshold Value in 64 bit words of the receive FIFO section full threshold Clear this field to enable store and forward on the RX FIFO When pro...

Страница 1189: ...zero 7 0 RX_ALMOST_ EMPTY Value of the receive FIFO almost empty threshold Value in 64 bit words of the receive FIFO almost empty threshold 46 3 25 Receive FIFO Almost Full Threshold ENET_RAFL Address...

Страница 1190: ...rds of the transmit FIFO section empty threshold 46 3 27 Transmit FIFO Almost Empty Threshold ENET_TAEM Address ENET_TAEM is 400C_0000h base 1A4h offset 400C_01A4h Bit 31 30 29 28 27 26 25 24 23 22 21...

Страница 1191: ...cy is required the value can be increased as necessary latency TAFL 5 NOTE A FIFO overflow is a fatal error and requires a global reset on the transmit datapath or at least deassertion of ETHER_EN 46...

Страница 1192: ...er when truncation occurs the application FIFO may receive less data guaranteeing that it never receives more than the set limit 46 3 31 Transmit Accelerator Function Configuration ENET_TACC TACC cont...

Страница 1193: ...to the transmit data FIFO that the written frames contain two additional octets before the frame data This means the actual frame starts at bit 16 of the first word written into the FIFO This functio...

Страница 1194: ...e value zero 2 PRODIS Enable discard of frames with wrong protocol checksum 0 Frames with wrong checksum are not discarded 1 If a TCP IP UDP IP or ICMP IP frame is received that has a wrong TCP UDP or...

Страница 1195: ...slave mode 0 The timer is active and all configuration bits in this register are relevant 1 The internal timer is disabled and the externally provided timer value is used All other bits except CAPTURE...

Страница 1196: ...besides clearing OFFEN when the offset is reached 1 If OFFEN is set the timer resets to zero when the offset setting is reached The offset event does not cause a timer interrupt 2 OFFEN Enable one sho...

Страница 1197: ...en in true nanoseconds 46 3 36 Timer Period Register ENET_ATPER Address ENET_ATPER is 400C_0000h base 40Ch offset 400C_040Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7...

Страница 1198: ...s ENET_ATINC is 400C_0000h base 414h offset 400C_0414h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 INC_CORR 0 INC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1199: ...h offset 400C_0604h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TF3 TF2 TF1 TF0 W w1c w1c w1c w1c Rese...

Страница 1200: ...0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TF TIE TMODE 0 TDRE W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENET_TCSRn field descriptions Field Description 31 8 Reserved This r...

Страница 1201: ...el is configured for Output Compare clear output on compare set output on overflow 10x1 Timer Channel is configured for Output Compare set output on compare clear output on overflow 1100 Reserved 1110...

Страница 1202: ...are value is less than the value of the IEEE 1588 Counter after the overflow then the compare occurs one 1588 clock cycle following the overflow When configured for Capture the value of the IEEE 1588...

Страница 1203: ...es RMON_T_P_GTE2048 0x244 RMON Tx Octets RMON_T_OCTETS 0x248 Count of frames not counted correctly IEEE_T_DROP NOTE Counter not implemented read 0 always as not applicable 0x24C Frames Transmitted OK...

Страница 1204: ...RMON_R_P65TO127 0x2B0 RMON Rx 128 to 255 byte packets RMON_R_P128TO255 0x2B4 RMON Rx 256 to 511 byte packets RMON_R_P256TO511 0x2B8 RMON Rx 512 to 1023 byte packets RMON_R_P512TO1023 0x2BC RMON Rx 102...

Страница 1205: ...f 64 bytes Maximum length of 1518 bytes excluding the preamble and the SFD bytes An Ethernet frame consists of the following fields Seven bytes preamble Start frame delimiter SFD Two address fields Le...

Страница 1206: ...e length type field indicates the length of the frame s payload section The most significant byte is sent received first If the length type field is set to a value less than 46 the payload is padded s...

Страница 1207: ...soon the current frame transfer is completed The MAC stops transmitting data for the value defined in pause quanta One pause quanta fraction refers to 512 bit times If a pause frame with a pause value...

Страница 1208: ...Datagram Format The following figure shows the IP Version 4 IPv4 header which is located at the beginning of an IP datagram It is organized in 32 bit words The first byte sent received is the leftmos...

Страница 1209: ...P header fields Source address Source IP address Destination address Destination IP address 46 4 2 3 IPv6 Datagram Format The following figure shows the IP version 6 IPv6 header which is located at th...

Страница 1210: ...6 defined extension header Hop limit Hop counter decremented by one by each station that forwards the frame If hop limit is 0 the frame must be discarded Source address 128 bit IPv6 source address Des...

Страница 1211: ...Length Checksum Table 46 64 UDP Header Fields Field Name Description Source port Source application port Destination port Destination application port Length Length of user data which follows immediat...

Страница 1212: ...e complete datagram TCP header and data and IP header information Options Additional 32 bit words for protocol options 46 4 3 IEEE 1588 Message Formats The following sections describe the IEEE 1588 me...

Страница 1213: ...v2 defines a native Ethernet frame format that uses ethertype 0x88F7 The payload of the Ethernet frame immediately contains the PTP datagram starting with the PTPv2 header Besides others version 2 add...

Страница 1214: ...ceUuid 28 2 sourcePortId 30 2 sequenceId 32 1 control 33 1 0x00 34 2 flags 36 4 reserved The type of message is encoded in the messageType and control fields as follows Table 46 71 PTPv1 Message Type...

Страница 1215: ...C Event message 0x1 DELAY_REQ Event message 0x2 PATH_DELAY_REQ Event message 0x3 PATH_DELAY_RESP Event message 0x4 0x7 reserved 0x8 FOLLOW_UP General message 0x9 DELAY_RESP General message 0xa PATH_DE...

Страница 1216: ...ine performs the following tasks Check frame framing Remove frame preamble and frame SFD field Frame discarding based on frame destination address field Terminate pause frames Check frame length Remov...

Страница 1217: ...on with an error and RxBD CE set 46 4 4 2 Preamble Processing The IEEE 802 3 standard allows a maximum size of 56 bits seven bytes for the preamble while the MAC core allows any arbitrary preamble len...

Страница 1218: ...ETn_IAUR IALR individual address hash match This mapping is performed by passing the 48 bit address through the on chip 32 bit CRC generator and selecting the six most significant bits of the CRC enco...

Страница 1219: ...he MAC operates in promiscuous mode and accepted a frame that would otherwise be rejected If a group individual hash or exact match does not occur and promiscuous mode is enabled RCR PROM 1 the frame...

Страница 1220: ...ays has the CRC error indication set RxBD CR 46 4 4 6 VLAN Frames Processing VLAN frames have a length type field set to 0x8100 immediately followed by a 16 Bit VLAN control information field VLAN tag...

Страница 1221: ...frame is marked invalid and RxBD CR is set 46 4 4 9 Frame Padding Removal When a frame is received with a payload length field set to less than 46 42 for VLAN tagged frames and 38 for frames with stac...

Страница 1222: ...ame if required Calculates and appends CRC 32 to the transmitted frame Send frame with correct inter packet gap IPG deferring When the MAC is configured to operate in half duplex mode the following ad...

Страница 1223: ...lynomial as specified in the 802 3 standard is FCS x x32 x26 x23 x22 x16 x12 x11 x10 x8 x7 x5 x4 x2 x1 1 The 32 bits of the CRC value are placed in the FCS field so that the x31 term is the right most...

Страница 1224: ...aving a jam pattern identical to the CRC If a collision occurs before transmission of 64 bytes including preamble and SFD the MAC core waits for the back off period and retransmits the packet data sto...

Страница 1225: ...re stops the current packet transmission and discards the rest of the packet from the transmit FIFO The core resumes transmission with the next packet available in the core transmit FIFO 46 4 6 Full D...

Страница 1226: ...threshold or when pause frame generation is requested by the local host processor To generate a pause frame the host processor sets ENETn_TCR TFC_PAUSE A single pause frame is generated when the curr...

Страница 1227: ...r application 46 4 7 Magic Packet Detection Magic packet detection wakes a node that is put is power down mode by the node management agent Magic packet detection is supported only if the MAC is confi...

Страница 1228: ...is detected EIR WAKEUP is set and none of the statistic registers are incremented 46 4 7 3 Wake up When a magic packet is detected indicated by ENETn_EIR WAKEUP ENETn_ECR SLEEP should be cleared to re...

Страница 1229: ...ed by subtracting the IP header length from the complete IP datagram length that is given in the IP header IPv4 or directly taken from the IP header IPv6 The protocol field is the corresponding value...

Страница 1230: ...ion can be enabled for transmit and receive independently with the corresponding SHIFT16 bits in the ENETn_TACC and ENETn_RACC registers When enabled the valid frame data is arranged as shown in this...

Страница 1231: ...IP frame with a valid IP header and a valid IP header checksum is detected the protocol is known but the protocol specific checksum is wrong If one of the errors occurs and the IP accelerator function...

Страница 1232: ...me If an IPv6 frame is received the first IP header is inspected first ten words which is available in every IPv6 frame If the receive SHIFT16 function is enabled the IP header is aligned on a 32 bit...

Страница 1233: ...O pointers A currently ongoing transmit is terminated by asserting MII_TXER to the PHY A currently ongoing transmit FIFO write from the application is terminated by stopping the write to the FIFO and...

Страница 1234: ...t Stop GTS When gracefully stopped the MAC is no longer reading frame data from the transmit FIFO and has completed any ongoing transmission In any of the following conditions the transmit datapath st...

Страница 1235: ...The MAC is in hardware freeze mode The MAC does not accept any frames from the MII When the receive datapath is stopped the following events occur If the RX is in the stopped state RCR GRS is set The...

Страница 1236: ...time stamping module to support precise time stamping of incoming and outgoing frames Set ENETn_ECR 1588EN to enable 1588 support Adjustable timer module Events generator User application Control Dat...

Страница 1237: ...Timer External free running counter ENET_ATPER ENET_ATCOR ENET_ATCR ENET_ATINC ENET_ATINC To MAC Figure 46 60 Adjustable Timer Implementation Detail The counter produces the current time During each t...

Страница 1238: ...en slave mode is enabled you still must set ENETn_ATINC INC to the value of the master since it is used for internal comparisons 46 4 10 2 Transmit Timestamping Only 1588 event frames need to be time...

Страница 1239: ...he timer to the remote master clock on the network The timer and all timestamp related information should be configured to show the true nanoseconds value of a second i e the timer is configured to ha...

Страница 1240: ...eceived the core receive read control stops the FIFO read and subsequently stops transferring data to the MAC client application It continues to deliver the frame if again more data than the threshold...

Страница 1241: ...f the application does not react on this signal the FIFO write control logic avoids FIFO overflow by truncating the current frame and setting the error status As a result the frame is transmitted with...

Страница 1242: ...FO MAC transmit FIFO write control FIFO write control TAFL Almost full TAEM Almost empty TSEM Section empty TFWR Section full MAC read control Core FIFO status MAC transmit start Figure 46 62 Transmit...

Страница 1243: ...s for each field NOTE The following addresses are shown for a big endian implementation Table 46 82 Legacy FEC Receive Buffer Descriptor RxBD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset 0 E RO1 W RO2...

Страница 1244: ...r fields To enable the enhanced features set ENETn_ECR 1588EN 46 4 14 1 Enhanced Receive Buffer Descriptor This section discusses the enhanced uDMA receive buffer descriptor NOTE The following address...

Страница 1245: ...in ENETn_RDSR Offset 0 12 RO2 Receive software ownership This field is reserved for use by software This read write bit is not modified by hardware nor does its value affect hardware Offset 0 11 L Las...

Страница 1246: ...0 Data Length Data length Written by the MAC Data length is the number of octets written by the MAC into this BD s data buffer if L is cleared the value is equal to EMRBR or the length of the frame in...

Страница 1247: ...his is an accelerator option This field is written by the uDMA This field is the sum of 32 bit words found within the IP and its following protocol headers If an IP datagram with an unknown protocol i...

Страница 1248: ...enhanced uDMA transmit buffer descriptor NOTE The following addresses are shown for a big endian implementation Table 46 86 Enhanced Transmit Buffer Descriptor TxBD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Страница 1249: ...t in the transmit frame 1 The buffer is the last in the transmit frame Offset 0 10 TC Transmit CRC Written by user only valid if L is set 0 End transmission immediately after the last data byte 1 Tran...

Страница 1250: ...E OE and TSE This bit is only valid when the L bit is set Offset A 14 Reserved must be cleared Offset A 13 UE Underflow error This bit is written by the uDMA This bit indicates that the MAC reported a...

Страница 1251: ...15 1 Data Structure Description The data structure defined in the following tables for the FIFO interface must be respected to ensure proper data transmission on the Ethernet line Byte 0 is sent to a...

Страница 1252: ...ETn_PAUR and ENETn_PALR registers Table 46 89 FIFO Interface Frame Format Byte Number Field 0 5 Destination MAC address 6 11 Source MAC address 12 13 Length type field 14 N Payload data VLAN tagged fr...

Страница 1253: ...ag 0x81 VLANinfo low VLAN info high VLAN tag 0x00 Figure 46 65 VLAN tagged Frame 64 bit Mapping Example If CRC forwarding is enabled CRCFWD 0 the last four valid octets of the frame contain the FCS fi...

Страница 1254: ...derflow when the application completes the frame transfer 3 the MAC transmit logic discards any new data available in the FIFO until the end of packet is reached 4 and sets the enhanced TxBD UE bit Th...

Страница 1255: ...ansmit FIFO overflows corrupting previously stored contents The core logic sets the enhanced TxBD OE bit for the next frame transmitted to indicate this overflow occurence Note Overflow is a fatal err...

Страница 1256: ...Frame available Data valid Start of packet End of packet RX data RX error RX error status 2 3 1 External signals Internal signals Figure 46 67 Receive FIFO Overflow Protection 46 4 17 PHY Management I...

Страница 1257: ...efines if a read or write operation is performed programmed with ENETn_MMFR OP 01 Write operation 10 Read operation Addr1 The PHY device address programmed with ENETn_MMFR PA Up to 32 devices can be a...

Страница 1258: ...face RMII 10 100 by way of interface converters gaskets The following table shows how to configure ENET registers to select each interface Mode ECR SPEED RCR RMII_10T RCR RMII_MODE MII 10Mbps1 0 0 MII...

Страница 1259: ...packet where the preamble is decoded RXD 1 0 01b RMII_REF_CLK RMII_CRS_DV 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 RMII_RXD1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMII_RXD0 False carrier detecte...

Страница 1260: ...9 1A 1C 1E 1F 20 21 22 23 24 25 26 27 28 29 2B 2E 2F 30 31 32 33 34 35 36 37 38 39 3B 3F 40 99 80 28 MII_TXER MII_TXCLK MII_TXD 3 0 MII_TXEN Figure 46 72 MII Transmit Operation If a frame is received...

Страница 1261: ...ation Transmission with Collision 46 4 18 3 MII Interface Receive On receive all signals are sampled on the MII_RXCLK rising edge The MII data enable signal MII_RXDV is asserted by the PHY to indicate...

Страница 1262: ...packet transfer CRC 32 SFD Preamble 5 MII_RXER MII_RXCLK MII_RXD 3 0 MII_RXDV Figure 46 76 MII Receive Operation Errored Frame A frame received on the MII interface with a PHY error indication is subs...

Страница 1263: ...a exchange between a host computer and a wide range of simultaneously accessible peripherals The attached peripherals share USB bandwidth through a host scheduled token based protocol The bus allows p...

Страница 1264: ...cation extends USB to peer to peer application Using USB OTG technology consumer electronics peripherals and portable devices can connect to each other for example a digital camera can connect directl...

Страница 1265: ...ints DMA or FIFO data stream interfaces Low power consumption On The Go protocol logic 47 2 Functional Description The USB FS 2 0 full speed low speed module communicates with the processor core throu...

Страница 1266: ...way allows the USB FS to easily transfer data at the maximum throughput provided by USB The software API intelligently manages buffers for the USB FS by updating the BDT when needed This allows the US...

Страница 1267: ...this reason a USB FS core centric nomenclature is used to describe the direction of the data transfer between the USB FS core and the USB Rx or receive describes transfers that move data from the USB...

Страница 1268: ...ed DMA controller to interrogate the BDT The USB FS reads the corresponding endpoint BD entry to determine if it owns the BD and corresponding buffer in system memory To compute the entry point in to...

Страница 1269: ...resides in system memory The format for the BD is shown in the following figure Table 47 3 Buffer Descriptor Byte Format 31 26 25 16 15 8 7 6 5 4 3 2 1 0 RSVD BC 10 bits RSVD OWN DATA0 1 KEEP TOK_PID...

Страница 1270: ...to prevent address increment 0 Bit 3 of the current token PID is written back in to the BD by the USB FS Allows the USB FS to release the BD when a token has been processed 1 This bit is unchanged by...

Страница 1271: ...an IN token 0xd for a SETUP token In host mode this field is used to report the last returned PID or a transfer status indication The possible values returned are 0x3 DATA0 0xb DATA1 0x2 ACK 0xe STALL...

Страница 1272: ...overflow This is predominantly a hardware performance issue usually caused by transient memory access issues Oversized Packets The packet received may be larger than the negotiated MaxPacket size Typi...

Страница 1273: ...ength field written back to the BDT is the MaxPacket value that represents the length of the clipped data actually written to memory From here the software can decide an appropriate course of action f...

Страница 1274: ...4007_20A0 Frame Number Register Low USB0_FRMNUML 8 R W 00h 47 4 17 1289 4007_20A4 Frame Number Register High USB0_FRMNUMH 8 R W 00h 47 4 18 1290 4007_20A8 Token Register USB0_TOKEN 8 R W 00h 47 4 19 1...

Страница 1275: ...ndpoint Control Register USB0_ENDPT13 8 R W 00h 47 4 23 1292 4007_20F8 Endpoint Control Register USB0_ENDPT14 8 R W 00h 47 4 23 1292 4007_20FC Endpoint Control Register USB0_ENDPT15 8 R W 00h 47 4 23...

Страница 1276: ...D Write Reset 1 1 1 1 1 0 1 1 USBx_IDCOMP field descriptions Field Description 7 6 Reserved This read only field is reserved and always has the value one These bits always read ones 5 0 NID Ones compl...

Страница 1277: ...changes of the ID sense and VBUS signals Software can read this register to determine which event has caused an interrupt Only bits that have changed since the last software read are set Writing a on...

Страница 1278: ...e OTG Interrupt Control Register enables the corresponding interrupt status bits defined in the OTG Interrupt Status Register Addresses USB0_OTGICR is 4007_2000h base 14h offset 4007_2014h Bit 7 6 5 4...

Страница 1279: ...ONEMSECEN LINESTATESTABLE 0 SESS_VLD BSESSEND 0 AVBUSVLD Write Reset 0 0 0 0 0 0 0 0 USBx_OTGSTAT field descriptions Field Description 7 ID Indicates the current state of the ID pin on the USB connect...

Страница 1280: ...A VBUS Valid threshold 1 The VBUS voltage is above the A VBUS Valid threshold 47 4 8 OTG Control Register USBx_OTGCTL The OTG Control Register controls the operation of VBUS and Data Line termination...

Страница 1281: ...All bits of this register are logically OR d together along with the OTG Interrupt Status Register OTGSTAT to form a single interrupt source for the processor s interrupt controller After an interrupt...

Страница 1282: ...onditions within the ERRSTAT register occur The processor must then read the ERRSTAT register to determine the source of the error 0 USBRST This bit is set when the USB Module has decoded a valid USB...

Страница 1283: ...T The Error Interrupt Status Register contains enable bits for each of the error sources within the USB Module Each of these bits are qualified with their respective error enable bits All bits of this...

Страница 1284: ...at data fields be an integral number of bytes If the data field was not an integral number of bytes this bit is set 2 CRC16 This bit is set when a data packet is rejected due to a CRC16 error 1 CRC5EO...

Страница 1285: ...enabled 1 The BTOERR interrupt is enabled 3 DFN8EN DFN8 Interrupt Enable 0 The DFN8 interrupt is not enabled 1 The DFN8 interrupt is enabled 2 CRC16EN CRC16 Interrupt Enable 0 The CRC16 interrupt is...

Страница 1286: ...on Clearing the TOKDNE bit in the ISTAT register causes the SIE to update the STAT register with the contents of the next STAT value If the data in the STAT holding register is valid the SIE immediate...

Страница 1287: ...ng token processing 4 RESET Setting this bit enables the USB Module to generate USB reset signaling This allows the USB Module to reset USB peripherals This control signal is only valid in Host mode H...

Страница 1288: ...register must be set The Address Register is reset to 0x00 after the reset input becomes active or the USB Module decodes a USB reset signal This action initializes the Address Register to decode add...

Страница 1289: ...ase address 0 Reserved This read only field is reserved and always has the value zero 47 4 17 Frame Number Register Low USBx_FRMNUML The Frame Number Register Low and High contains an 11 bit value use...

Страница 1290: ...ripheral it writes the TOKEN type and endpoint to this register After this register has been written the USB module begins the specified USB transaction to the address contained in the address registe...

Страница 1291: ...n packet transactions This register must be set to a value that ensures that other packets are not actively being transmitted when the SOF time counts to zero When the SOF counter reaches the threshol...

Страница 1292: ...esides in system memory Addresses USB0_BDTPAGE3 is 4007_2000h base B4h offset 4007_20B4h Bit 7 6 5 4 3 2 1 0 Read BDTBA Write Reset 0 0 0 0 0 0 0 0 USBx_BDTPAGE3 field descriptions Field Description 7...

Страница 1293: ...NAK ed Negative Acknowledgement transactions When a transaction is NAKed the BDT PID field is updated with the NAK PID and the TOKEN_DNE interrupt is set When this bit is cleared NAKed transactions i...

Страница 1294: ...TG Observe Register USBx_OBSERVE Provides visibility on the state of the pull ups and pull downs at the transceiver Useful when interfacing to an external OTG control module via a serial interface Add...

Страница 1295: ..._CONTROL is 4007_2000h base 108h offset 4007_2108h Bit 7 6 5 4 3 2 1 0 Read 0 DPPULLUPNONOTG 0 Write Reset 0 0 0 0 0 0 0 0 USBx_CONTROL field descriptions Field Description 7 5 Reserved This read only...

Страница 1296: ...enables clocks to the USB module It is used for low power suspend mode when USB module clocks are stopped or the USB transceiver is in Suspend mode Async wakeup only works in device mode 0 USB asynch...

Страница 1297: ...but the number of ISO streams that can be practically supported is affected by the interrupt latency of the processor servicing the token during interrupts from the SIE Custom drivers must be written...

Страница 1298: ...2 Set up the endpoint control register for bidirectional control transfers EP_CTL0 4 0 0x0d 3 Place a copy of the device framework setup command in a memory buffer Refer to the Universal Serial Bus R...

Страница 1299: ...of the setup transaction Refer to the Universal Serial Bus Revision 2 0 specification Chapter 9 USB Device Framework http www usb org developers docs 10 To initiate the Status phase of the setup tran...

Страница 1300: ...sor and that the transfer has completed If the target device asserts NAKs the USB FS continues to retry the transfer indefinitely without processor intervention unless the RETRY_DIS retry disable bit...

Страница 1301: ...t The cable has been un plugged or a Type B cable has been attached The device now acts as a Type B device Go to B_IDLE If the A application wants to use the bus or if the B device is doing an SRP as...

Страница 1302: ..._SUSPEND If ID Interrupt or if 150 msec B disconnect timeout This timeout value could be longer or if A_VBUS_VLD Interrupt Go to A_WAIT_VFALL Turn off DRV_VBUS If HNP enabled and B disconnects in 150...

Страница 1303: ...pt or SRP Done SRP must be done in less than 100 msecs Go to B_IDLE B_PERIPHERAL If HNP enabled and the bus is suspended and B wants the bus the B device can become the host Go to B_WAIT_ACON Turn off...

Страница 1304: ...On The Go Operation K53 Sub Family Reference Manual Rev 6 Nov 2011 1304 Freescale Semiconductor Inc...

Страница 1305: ...and abbreviations used in this document Table 48 1 Acronyms and Abbreviated Terms Term Meaning FS Full Speed 12 Mbps HS High Speed 480 Mbps IDEV_DCHG Current drawn when the USB device is connected to...

Страница 1306: ...lup resistor Connected Device is physically plugged into USB port and has enabled either D or D pullup resistor Suspended After 3 ms of no bus activity the USB device enters suspend mode Component The...

Страница 1307: ...urrent source current sink and voltage comparator circuitry 48 2 2 Features The USBDCD module offers the following features Compliant with the latest industry standard specification USB Battery Chargi...

Страница 1308: ...system performance requirements allow putting the device into a very low power stop mode Operating mode transitions are shown in the following table Table 48 4 Entering and Exiting Module Modes Module...

Страница 1309: ...sceiver module also interfaces to usb_dm and usb_dp Both modules and the USB host hub use these signal as bi directional tri state signals Information about the signal integrity aspects of the lines i...

Страница 1310: ...offset 4003_5000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 IE W SR START Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved IF 0 0 W IACK...

Страница 1311: ...terrupt Flag Determines whether an interrupt is pending 0b0 No interrupt is pending 0b1 An interrupt is pending 7 1 Reserved This read only field is reserved and always has the value zero 0 IACK Inter...

Страница 1312: ...erved and always has the value zero 0 CLOCK_UNIT Unit of measurement encoding for Clock Speed Specifies the unit of measure for the clock speed 0b0 kHz Speed between 1 kHz and 1023 kHz 0b1 MHz Speed b...

Страница 1313: ...tatus of the charger detection sequence 0b00 The module is either not enabled or the module is enabled but the data pins have not yet been detected 0b01 Data pin contact detection is complete 0b10 Cha...

Страница 1314: ...n sequence in the USBDCD module When software sets the CONTROL START bit the Unit Connection Timer TUNITCON is initialized with the value of TSEQ_INIT Valid values are 0 1023 but the USB Battery Charg...

Страница 1315: ...in ms that VDP_SRC IDM_SINK and the D VDAT_REF comparator are enabled and connected to the D D lines during the charging port detection phase of the sequence Valid values are 1 1023 but the USB Batte...

Страница 1316: ...harging port Valid values are 1 15ms 48 5 Functional Description The sequence of detecting the presence of and type of charging port involves several hardware components coordinated by system software...

Страница 1317: ...s for the USB D and D signals The D pullup and the D pulldown are both used during the charger detection sequence The USB transceiver also outputs the digital state of the D and D signals from the USB...

Страница 1318: ...NC C H E C K _D M Dedicated Charger C harging H ost D edicated C harger C harging H ost TVDPSRC_ON TVDPSRC_CON TCON_IDPSNK_DIS TVDMSRC_DIS Standard host VD VDAT REF T VDMSRC_EN lgc_hi lgc_lo off on of...

Страница 1319: ...quence will continue until halted by software Charger Detection Sequence Timeout Timing parameter values used in this module are listed in the following table Table 48 15 Timing Parameters for the Cha...

Страница 1320: ...ialize the module and start the charger detection sequence 1 Restore power if the module is powered off 2 Set the CONTROL SR bit to initiate a software reset 3 Configure the USBDCD module Program the...

Страница 1321: ...ow and debouncing begins Once the D line goes low the module continuously samples the D line over the duration of the TDCD_DBNC debounce time interval TDCD_DBNC defaults to 10 ms but can be programmed...

Страница 1322: ...ammable and defaults to 40 ms After sampling the D line the module disconnects the voltage source current sink and comparator The next steps in the sequence depend on the voltage on the D line as dete...

Страница 1323: ...the TVDPSRC_CON interval has elapsed before doing the following Updates the STATUS register to reflect that a charging port has been detected with SEQ_RES 10 See Table 48 18 for field values Sets the...

Страница 1324: ...e is notified automatically via internal signaling the module waits until the ipp_pue_pullup_dp input goes high to start the CHECK_DM timer counting down the time interval programmed into the TIMER2 C...

Страница 1325: ...arge rate to the external battery charger IC see Table 48 13 48 5 1 5 2 Charging Host Port For a charging host port the module does the following Updates the STATUS register to reflect that a charging...

Страница 1326: ...e the interrupt and allow more time for the sequence to complete or halt the sequence To halt the sequence software should 1 Read the STATUS register 2 Set the CONTROL IACK bit to acknowledge the inte...

Страница 1327: ...rror The module cannot identify the type of port because the D line is above the USB s VLGC threshold ERR 1 SEQ_STAT 10 SEQ_RES 00 TO 0 Error in Charging Port Detection Charger Type Detection Phase Co...

Страница 1328: ...er hardware reset sources Hardware resets cause the register contents to be restored to their default state as listed in the register descriptions 48 5 3 2 Software Reset A software reset re initializ...

Страница 1329: ...ver several timing parameters can be changed for a great deal of flexibility if a particular system requires it All module configuration must occur before initiating the charger detection sequence Con...

Страница 1330: ...these systems if it is known that the battery is weak or dead software can delay connecting to the USB while charging at 1 5A Once the battery is charged to the good battery threshold software can th...

Страница 1331: ...wer supply varying from 2 7 V to 5 5 V It consists of one 3 3 V power channel When the input power supply is below 3 6 V the regulator goes to pass through mode The following figure shows the ideal re...

Страница 1332: ...are also enabled but a switch disconnects its output from the external pin In STANDBY mode the RUN regulator is disabled and the STANDBY regulator output is connected to the external pin supplying up...

Страница 1333: ...he regulating loop of the RUN regulator is disabled and the standby regulator is active The switch connecting the STANDBY regulator output to the external pin is closed SHUTDOWN The module is disabled...

Страница 1334: ...USB Voltage Regulator Module Signal Descriptions K53 Sub Family Reference Manual Rev 6 Nov 2011 1334 Freescale Semiconductor Inc...

Страница 1335: ...the chip configuration chapter The serial peripheral interface module provides a synchronous serial bus for communication between an MCU and an external peripheral device 50 1 1 Block Diagram The bloc...

Страница 1336: ...sfers Master and slave modes Data streaming operation in slave mode with continuous slave selection Buffered transmit operation using the TX FIFO with depth of 4 entries Buffered receive operation usi...

Страница 1337: ...to TX FIFO and removing entries from RX FIFO TX FIFO is not full TFFF RX FIFO is not empty RFDF Interrupt conditions End of queue reached EOQF TX FIFO is not full TFFF Transfer of current frame comple...

Страница 1338: ...al to the DSPI Data transfers between the queues and the DSPI FIFOs are accomplished by a DMA controller or host CPU The following figure shows a system example with DMA DSPI and external queues in sy...

Страница 1339: ...ally controlled serial transfers The SCK signal and the PCS 0 SS signals are configured as inputs and driven by a SPI bus master 50 1 4 3 Module Disable Mode The module disable mode can be used for MC...

Страница 1340: ...lect input I O PCS 3 1 Master mode Peripheral Chip Select 1 3 Slave mode Unused O PCS4 Master mode Peripheral Chip Select 4 Slave mode Unused O PCS5 PCSS Master mode Peripheral Chip Select 5 Periphera...

Страница 1341: ...device the current transfer is intended for When the DSPI is in master mode and the MCR PCSSE bit is set the PCSS signal acts as a strobe to an external peripheral chip select demultiplexer which dec...

Страница 1342: ...SPI0_SR 32 R W See section 50 3 5 1354 4002_C030 DSPI DMA Interrupt Request Select and Enable Register SPI0_RSER 32 R W 0000_0000h 50 3 6 1357 4002_C034 DSPI PUSH TX FIFO Register In Master Mode SPI0_...

Страница 1343: ...st Select and Enable Register SPI1_RSER 32 R W 0000_0000h 50 3 6 1357 4002_D034 DSPI PUSH TX FIFO Register In Master Mode SPI1_PUSHR 32 R W 0000_0000h 50 3 7 1359 4002_D034 DSPI PUSH TX FIFO Register...

Страница 1344: ...I PUSH TX FIFO Register In Master Mode SPI2_PUSHR 32 R W 0000_0000h 50 3 7 1359 400A_C034 DSPI PUSH TX FIFO Register In Slave Mode SPI2_PUSHR_SLAVE 32 R W 0000_0000h 50 3 8 1361 400A_C038 DSPI POP RX...

Страница 1345: ...0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DOZE MDIS DIS_TXF DIS_RXF 0 0 SMPL_PT 0 0 HALT W CLR_ TXF CLR_ RXF Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SPIx_MCR...

Страница 1346: ...ceived the data from the transfer generating the overflow is ignored or shifted into the shift register 0 Incoming data is ignored 1 Incoming data is shifted into the shift register 23 22 Reserved Thi...

Страница 1347: ...r the Tx FIFO counter 1 Clear the Tx FIFO counter 10 CLR_RXF Flushes the RX FIFO Writing a 1 to CLR_RXF clears the RX Counter The CLR_RXF bit is always read as zero 0 Do not clear the Rx FIFO counter...

Страница 1348: ...eld is set in the executing SPI command The Transfer Counter wraps around incrementing the counter past 65535 resets the counter to zero 15 0 Reserved This read only field is reserved and always has t...

Страница 1349: ...K This field is used only in master mode It effectively halves the Baud Rate division ratio supporting faster frequencies and odd division ratios for the Serial Communications Clock SCK When the DBR b...

Страница 1350: ...captured on the leading edge of SCK and changed on the following edge 1 Data is changed on the leading edge of SCK and captured on the following edge 24 LSBFE LBS First Specifies whether the LSB or M...

Страница 1351: ...lue before the baud rate selection takes place See the BR field description for details on how to compute the baud rate 00 Baud Rate Prescaler value is 2 01 Baud Rate Prescaler value is 3 10 Baud Rate...

Страница 1352: ...S signal at the end of a frame and the assertion of PCS at the beginning of the next frame In the Continuous Serial Communications Clock operation the DT value is fixed to one SCK clock period The Del...

Страница 1353: ...e Ch offset 400A_C00Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R FMSZ CPOL CPHA 0 0 W Reset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1354: ...us and flag bits The bits reflect the status of the DSPI and indicate the occurrence of events that can generate interrupt or DMA requests Software can clear flag bits in the SR by writing a 1 to them...

Страница 1355: ...condition in the TX FIFO The transmit underflow condition is detected only for DSPI blocks operating in slave mode and SPI configuration TFUF is set when the TX FIFO of a DSPI operating in SPI slave m...

Страница 1356: ...s empty 1 Rx FIFO is not empty 16 Reserved This read only field is reserved and always has the value zero 15 12 TXCTR TX FIFO Counter Indicates the number of valid entries in the TX FIFO The TXCTR is...

Страница 1357: ...tion 31 TCF_RE Transmission Complete Request Enable Enables TCF flag in the SR to generate an interrupt request 0 TCF interrupt requests are disabled 1 TCF interrupt requests are enabled 30 Reserved T...

Страница 1358: ...read only field is reserved and always has the value zero 20 Reserved This read only field is reserved and always has the value zero 19 RFOF_RE Receive FIFO Overflow Request Enable Enables the RFOF f...

Страница 1359: ...12 11 10 9 8 7 6 5 4 3 2 1 0 R CONT CTAS EOQ CTCNT 0 0 PCS 5 0 TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIx_PUSHR field descriptions Field Description 31 CONT Co...

Страница 1360: ...s transmitting the current SPI frame 0 Do not clear the TCR SPI_TCNT field 1 Clear the TCR SPI_TCNT field 25 24 Reserved This read only field is reserved and always has the value zero 23 22 Reserved T...

Страница 1361: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R TXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIx_PUSHR_SLAVE field descriptions Field Description 31 0 TXDATA Transmit Data...

Страница 1362: ...Description 31 16 TXCMD_ TXDATA Transmit Command or Transmit Data In master mode the TXCMD field contains the command that sets the transfer attributes for the SPI data In slave mode the TXDATA conta...

Страница 1363: ...to use on a frame by frame basis by setting a field in the SPI command See DSPI Clock and Transfer Attributes Registers for information on the fields of the CTAR registers Typical master to slave con...

Страница 1364: ...transfers are responded to in slave mode The STOPPED state is also a safe state for writing the various configuration registers of the DSPI without causing undetermined results In the RUNNING state se...

Страница 1365: ...to the DSPI and the SPI command field space is used for 16 most significant bit of the transmit data 50 4 2 1 Master Mode In SPI master mode the DSPI initiates the serial transfers by controlling the...

Страница 1366: ...he TX FIFO holds 4 words each consisting of a command field and a data field The number of entries in the TX FIFO is device specific SPI commands and data are added to the TX FIFO by writing to the DS...

Страница 1367: ...DSPI slave while the slave s DSPI TX FIFO is empty the Transmit FIFO Underflow Flag TFUF in the slave s SR is set See Transmit FIFO Underflow Interrupt Request for details 50 4 2 5 Receive First In Fi...

Страница 1368: ...ata is ignored 50 4 2 5 2 Draining the RX FIFO Host CPU or a DMA can remove pop entries from the RX FIFO by reading the DSPI POP RX FIFO Register POPR A read of the POPR decrements the RX FIFO Counter...

Страница 1369: ...ocking chapter for the frequency used to drive this module in the device 50 4 3 2 PCS to SCK Delay tCSC The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edg...

Страница 1370: ...een negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame See Figure 50 94 for an illustration of the Delay after Transfer The PDT and DT fields in the CTARx re...

Страница 1371: ...the PCSSCK field in the CTAR based on the following formula At the end of the transfer the delay between PCSS negation and PCS negation is selected by the PASC field in the CTAR based on the followin...

Страница 1372: ...en though the bus slave does not control the SCK signal in slave mode these values must be identical to the master device settings to ensure proper transmission In SPI slave mode only CTAR0 is used Th...

Страница 1373: ...The master initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate peripheral chip select signals to the slave device The slave responds by placing its first...

Страница 1374: ...it 4 Bit 3 Bit 2 Bit 1 LSB first LSBFE 1 LSB Figure 50 95 DSPI Transfer Timing Diagram MTFE 0 CPHA 1 FMSZ 8 The master initiates the transfer by asserting the PCS signal to the slave After the tCSC de...

Страница 1375: ...ates in between frames The idle states of the Chip Select signals are selected by the PCSISn bits in the MCR The following timing diagram is for two four bit transfers with CPHA 1 and CONT 0 PCSx SCK...

Страница 1376: ...s the PCSn at end of transmission of last frame The PUSHR CONT DSICR0 DCONT bits must be de asserted before asserting MCR HALT bit in master mode This will make sure that the PCSn signals are de asser...

Страница 1377: ...CTAS for the frame is used In all configurations the currently selected CTAR remains in use until the start of a frame with a different CTAR specified or the Continuous SCK mode is terminated It is re...

Страница 1378: ...nclude Continuous SCK with CONT bit set but no data in the transmit FIFO Continuous SCK with CONT bit set and entering STOPPED state refer to Start and Stop of DSPI Transfers Continuous SCK with CONT...

Страница 1379: ...meSize is the value of the CTAR0 1 FMSZ field plus one 3 50 4 7 Interrupts DMA Requests The DSPI has several conditions that can only generate interrupt requests and two conditions that can generate i...

Страница 1380: ...ible entries and the TFFF_RE bit in the RSER is set The TFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is generated NOTE TFFF flag clears automatically when DMA is use...

Страница 1381: ...selects whether a DMA request or an interrupt request is generated 50 4 7 6 Receive FIFO Overflow Interrupt Request The Receive FIFO Overflow Request indicates that an overflow condition in the RX FIF...

Страница 1382: ...lock to the non memory mapped logic When Clock Enable is negated the DSPI is in a dormant state but the memory mapped registers are still accessible Certain read or write operations have a different e...

Страница 1383: ...fter each read operation of the POPR 7 Modify DMA descriptor of TX and RX channels for new queues 8 Flush TX FIFO by writing a 1 to the CLR_TXF bit in the MCR Flush RX FIFO by writing a 1 to the CLR_R...

Страница 1384: ...5M 8 33M 5 00M 3 57M 6 8 33M 5 56M 3 33M 2 38M 8 6 25M 4 17M 2 50M 1 79M 16 3 12M 2 08M 1 25M 893k 32 1 56M 1 04M 625k 446k 64 781k 521k 312k 223k 128 391k 260k 156k 112k 256 195k 130k 78 1k 55 8k 51...

Страница 1385: ...2 3 ms 65536 655 4 s 2 0 ms 3 3 ms 4 6 ms 50 5 5 Calculation of FIFO Pointer Addresses Complete visibility of the TX and RX FIFO contents is available through the FIFO registers and valid entries can...

Страница 1386: ...llowing equation The memory address of the last in entry in the TX FIFO is computed by the following equation TX FIFO Base Base address of TX FIFO TXCTR TX FIFO Counter TXNXTPTR Transmit Next Pointer...

Страница 1387: ...y the following equation RX FIFO Base Base address of RX FIFO RXCTR RX FIFO counter POPNXTPTR Pop Next Pointer RX FIFO Depth Receive FIFO depth implementation specific Chapter 50 SPI DSPI K53 Sub Fami...

Страница 1388: ...Initialization Application Information K53 Sub Family Reference Manual Rev 6 Nov 2011 1388 Freescale Semiconductor Inc...

Страница 1389: ...a maximum bus capacitance of 400 pF The I2C module also complies with the System Management Bus SMBus Specification version 2 51 1 1 Features The I2C module has the following features Compatible with...

Страница 1390: ...this mode disable the module Wait mode The module continues to operate when the core is in wait mode and can provide a wakeup interrupt Stop mode The module is inactive in stop mode for reduced power...

Страница 1391: ...ptions The signal properties of I2C are shown in the following table Table 51 1 I2C Signal Descriptions Signal Description I O SCL Bidirectional serial clock line of the I2C system I O SDA Bidirection...

Страница 1392: ...401 4006_6009 I2C Address Register 2 I2C0_A2 8 R W C2h 51 3 10 1402 4006_600A I2C SCL Low Timeout Register High I2C0_SLTH 8 R W 00h 51 3 11 1403 4006_600B I2C SCL Low Timeout Register Low I2C0_SLTL 8...

Страница 1393: ...2C1_A1 is 4006_7000h base 0h offset 4006_7000h Bit 7 6 5 4 3 2 1 0 Read AD 7 1 0 Write Reset 0 0 0 0 0 0 0 0 I2Cx_A1 field descriptions Field Description 7 1 AD 7 1 Address Contains the primary slave...

Страница 1394: ...hold time bus period s mul SDA hold value The SCL start hold time is the delay from the falling edge of SDA I2C data while SCL is high start condition to the falling edge of SCL I2C clock SCL start ho...

Страница 1395: ...oth master and slave receivers The value of the FACK bit affects NACK ACK generation 0 An acknowledge signal is sent to the bus on the following if FACK is cleared or current if FACK is set receiving...

Страница 1396: ...ions Field Description 7 TCF Transfer complete flag This bit sets on the completion of a byte and acknowledge bit transfer This bit is valid only during or immediately following a transfer to or from...

Страница 1397: ...When addressed as a slave SRW indicates the value of the R W command bit of the calling address sent to the master 0 Slave receive master writing to slave 1 Slave transmit master reading from slave 1...

Страница 1398: ...functions are available after an address match occurs The C1 TX bit must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin For example if the...

Страница 1399: ...ave baud rate follows the master baud rate and clock stretching may occur 1 Slave baud rate is independent of the master baud rate 3 RMEN Range address matching enable This bit controls slave address...

Страница 1400: ...ass 00h No filter bypass 01 1Fh Filter glitches up to width of n bus clock cycles where n 1 31d 51 3 8 I2C Range Address register I2Cx_RA Addresses I2C0_RA is 4006_6000h base 7h offset 4006_6007h I2C1...

Страница 1401: ...eld Description 7 FACK Fast NACK ACK enable For SMBus packet error checking the CPU must be able to issue an ACK or NACK according to the result of receiving data byte 0 An ACK or NACK is sent on the...

Страница 1402: ...ag 1 This read only bit sets when SCL and SDA are held high more than clock LoValue 512 which indicates the bus is free This bit is cleared automatically 0 No SCL high and SDA high timeout occurs 1 SC...

Страница 1403: ...t 0 0 0 0 0 0 0 0 I2Cx_SLTH field descriptions Field Description 7 0 SSLT 15 8 Most significant byte of SCL low timeout value that determines the timeout period of SCL low 51 3 12 I2C SCL Low Timeout...

Страница 1404: ...ld not be confused with the CPU STOP instruction The following figure illustrates I2C bus system communication S C L S D A D 0 D ata B yte N ew C alling A ddress X X W rite C alling A ddress W rite W...

Страница 1405: ...two slaves in the system can have the same address If the I2C module is the master it must not transmit an address that is equal to its own slave address The I2C module cannot be master and slave at...

Страница 1406: ...must release the bus 51 4 1 5 Repeated START Signal The master may generate a START signal followed by a calling command without generating a STOP signal first This action is called a repeated START...

Страница 1407: ...horter low periods enter a high wait state during this time see the following diagram When all applicable devices have counted off their low period the synchronized clock SCL is released and pulled hi...

Страница 1408: ...10 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161...

Страница 1409: ...n is not changed When a 10 bit address follows a START condition each slave compares the first seven bits of the first byte of the slave address 11110XX with its own address and tests whether the eigh...

Страница 1410: ...ve devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth R W bit However none of them are addressed because R W 1 for 10 bit dev...

Страница 1411: ...accept control parameters and return its status 51 4 4 1 Timeouts The TTIMEOUT MIN parameter allows a master or slave to conclude that a defective device is holding the clock low indefinitely or a ma...

Страница 1412: ...me the bus is free when SHTF1 rises A HIGH timeout occurs in scenario 2 if a master ever detects that both the BUSY bit is high and SHTF1 is high When the SMBDAT signal is low and the SMBCLK signal is...

Страница 1413: ...dress resolution protocol ARP process The PEC is a CRC 8 error checking byte calculated on all the message bytes The PEC is appended to the message by the device that supplied the last data byte If th...

Страница 1414: ...t is set The interrupt is driven by the IICIF bit of the I2C Status Register and masked with the IICIE bit of the I2C Control Register 1 The IICIF bit must be cleared by software by writing 1 to it in...

Страница 1415: ...f low power stop mode if the interrupt is not masked Therefore TCF and IAAS both can trigger this interrupt 51 4 6 4 Arbitration Lost Interrupt The I2C is a true multimaster bus that allows more than...

Страница 1416: ...nes for the I2C module The width of the glitch to absorb can be specified in terms of the number of half bus clock cycles A single Programmable Input Glitch Filter control register is provided Effecti...

Страница 1417: ...MA transfer NOTE Before the last byte of master receive mode TXAK must be set to send a NACK after the last byte s transfer Therefore the DMA must be disabled before the last byte s transfer NOTE In 1...

Страница 1418: ...Control Register 1 to enable MST master mode 7 Write Data register with the address of the target slave the LSB of this byte determines whether the communication is master receive or transmit The rou...

Страница 1419: ...om Data reg N Y N N N N N N Y Y Y Y Y read N write N Y Rx Tx Rx Tx Y N Address transfer see note 1 Data transfer see note 2 N Y Y Y Notes 1 If general call is enabled check to determine if the receive...

Страница 1420: ...F FACK 1 N Y See typical I2C interrupt routine flow chart Set TXAK to proper value Clear IICIF Delay note 2 Set Tx mode Write data to Data reg Clear IICIF Notes 1 If general call or SIICAEN is enabled...

Страница 1421: ...features Full duplex operation Standard mark space non return to zero NRZ format Selectable IrDA 1 4 return to zero inverted RZI format with programmable pulse widths 13 bit baud rate selection with...

Страница 1422: ...f NACK d packets with programmable retry threshold Support for 11 and 12 ETU transfers Detection of initial packet and automated transfer parameter programming Interrupt driven operation with seven IS...

Страница 1423: ...s It has two low power modes Wait and Stop modes 52 1 2 1 Run mode This is the normal mode of operation 52 1 2 2 Wait mode UART operation in wait mode depends on the state of the C1 UARTSWAI bit If th...

Страница 1424: ...gister states but the UART module clock will be disabled The UART operation resumes from where it left off after an external interrupt brings the CPU out of stop mode Exiting stop mode by reset aborts...

Страница 1425: ...an deassert asynchronously to the other input signals RXD I Receive data Serial data input to receiver State meaning Whether RXD is interpreted as a 1 or 0 depends on the bit encoding method along wit...

Страница 1426: ...A009 UART Match Address Registers 2 UART0_MA2 8 R W 00h 52 3 10 1449 4006_A00A UART Control Register 4 UART0_C4 8 R W 00h 52 3 11 1450 4006_A00B UART Control Register 5 UART0_C5 8 R W 00h 52 3 12 1451...

Страница 1427: ...0_WF7816 8 R W 01h 52 3 29 1469 4006_A01E UART 7816 Error Threshold Register UART0_ET7816 8 R W 00h 52 3 30 1470 4006_A01F UART 7816 Transmit Length Register UART0_TL7816 8 R W 00h 52 3 31 1471 4006_B...

Страница 1428: ...Transmit Watermark UART1_TWFIFO 8 R W 00h 52 3 19 1459 4006_B014 UART FIFO Transmit Count UART1_TCFIFO 8 R 00h 52 3 20 1460 4006_B015 UART FIFO Receive Watermark UART1_RWFIFO 8 R W 01h 52 3 21 1460 40...

Страница 1429: ...446 4006_C007 UART Data Register UART2_D 8 R W 00h 52 3 8 1447 4006_C008 UART Match Address Registers 1 UART2_MA1 8 R W 00h 52 3 9 1449 4006_C009 UART Match Address Registers 2 UART2_MA2 8 R W 00h 52...

Страница 1430: ...ter UART2_WP7816T1 8 R W 0Ah 52 3 27 1468 4006_C01C UART 7816 Wait N Register UART2_WN7816 8 R W 00h 52 3 28 1469 4006_C01D UART 7816 Wait FD Register UART2_WF7816 8 R W 01h 52 3 29 1469 4006_C01E UAR...

Страница 1431: ..._CFIFO 8 R W 00h 52 3 17 1457 4006_D012 UART FIFO Status Register UART3_SFIFO 8 R W C0h 52 3 18 1458 4006_D013 UART FIFO Transmit Watermark UART3_TWFIFO 8 R W 00h 52 3 19 1459 4006_D014 UART FIFO Tran...

Страница 1432: ...ster 1 UART4_S1 8 R C0h 52 3 5 1441 400E_A005 UART Status Register 2 UART4_S2 8 R W 00h 52 3 6 1444 400E_A006 UART Control Register 3 UART4_C3 8 R W 00h 52 3 7 1446 400E_A007 UART Data Register UART4_...

Страница 1433: ...E_A01B UART 7816 Wait Parameter Register UART4_WP7816T0 8 R W 0Ah 52 3 26 1467 400E_A01B UART 7816 Wait Parameter Register UART4_WP7816T1 8 R W 0Ah 52 3 27 1468 400E_A01C UART 7816 Wait N Register UAR...

Страница 1434: ...frared Register UART5_IR 8 R W 00h 52 3 15 1454 400E_B010 UART FIFO Parameters UART5_PFIFO 8 R W See section 52 3 16 1455 400E_B011 UART FIFO Control Register UART5_CFIFO 8 R W 00h 52 3 17 1457 400E_B...

Страница 1435: ...w value and then write to BDL The working value in BDH does not change until BDL is written BDL is reset to a non zero value but after reset the baud rate generator remains disabled until the first ti...

Страница 1436: ...y location until BDL is written 52 3 2 UART Baud Rate Registers Low UARTx_BDL This register along with the BDH register controls the prescale divisor for UART baud rate generation To update the 13 bit...

Страница 1437: ...h base 2h offset 4006_D002h UART4_C1 is 400E_A000h base 2h offset 400E_A002h UART5_C1 is 400E_B000h base 2h offset 400E_B002h Bit 7 6 5 4 3 2 1 0 Read LOOPS UARTSWAI RSRC M WAKE ILT PE PT Write Reset...

Страница 1438: ...perly synchronized transmissions NOTE In the case where UART is programmed with ILT 1 a logic of 1 b0 is automatically shifted after a received stop bit thus resetting the idle count NOTE In the case...

Страница 1439: ...n outside of servicing of a DMA request 0 TDRE interrupt and DMA transfer requests disabled 1 TDRE interrupt or DMA transfer requests enabled 6 TCIE Transmission Complete Interrupt Enable TCIE enables...

Страница 1440: ...idle This can be determined by the S2 RAF flag If set to wake up an IDLE event and the channel is already idle it is possible that the UART will discard data since data must be received or a LIN break...

Страница 1441: ...l the flag will reassert and generate another interrupt or DMA request NOTE Reading an empty data register to clear one of these flags causes the FIFO pointers to get out of alignment A receive FIFO f...

Страница 1442: ...d in the count RDRF is prevented from setting while S2 LBKDE is set Additionally when S2 LBKDE is set datawords that are received will be stored in the receive buffer but will over write each other To...

Страница 1443: ...was cleared If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise 1 At least one dataword was received with noise detected since t...

Страница 1444: ...onsecutive logic 0s if C1 M 1 appear on the receiver input LBKDIF is set right after receiving the last LIN break character bit LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been...

Страница 1445: ...E is set enabled 0 The S1 IDLE bit is not set upon detection of an idle character 1 The S1 IDLE bit is set upon detection of an idle character 2 BRK13 Break Transmit Character Length This bit determin...

Страница 1446: ...when the UART is configured for 9 bit data format C1 M 1 or C4 M10 1 6 T8 Transmit Bit 8 T8 is the ninth data bit transmitted when the UART is configured for 9 bit data format C1 M 1 or C4 M10 1 NOTE...

Страница 1447: ...only the transmitted data bits and parity bit are inverted 0 Transmit data is not inverted 1 Transmit data is inverted 3 ORIE Overrun Error Interrupt Enable This bit enables the overrun error flag S1...

Страница 1448: ...ing 8 bit write instructions write first to transmit bit 8 in UART control register 3 C3 T8 then D A write to C3 T8 stores the data in a temporary register If D register is written first then the new...

Страница 1449: ...x_MA1 field descriptions Field Description 7 0 MA Match Address 52 3 10 UART Match Address Registers 2 UARTx_MA2 These registers can be read and written at anytime The MA1 and MA2 registers are compar...

Страница 1450: ...transferred to the data buffer This bit must be cleared when C7816 ISO7816E is set enabled 6 MAEN2 Match Address Mode Enable 2 Refer to Match address operation for more information 0 All data received...

Страница 1451: ...MA Select TDMAS configures the transmit data register empty flag S1 TDRE to generate interrupt or DMA requests if C2 TIE is set NOTE If C2 TIE is cleared TDRE DMA and TDRE interrupt request signals ar...

Страница 1452: ...eive FIFO NOTE The data contained in this register represents additional information regarding the conditions on which a dataword was received The importance of this data varies with application and i...

Страница 1453: ...e ISO 7816 protocol does not make use of the RTS and CTS signals Addresses UART0_MODEM is 4006_A000h base Dh offset 4006_A00Dh UART1_MODEM is 4006_B000h base Dh offset 4006_B00Dh UART2_MODEM is 4006_C...

Страница 1454: ...r are completely sent including the last stop bit 0 TXCTSE Transmitter clear to send enable TXCTSE controls the operation of the transmitter TXCTSE can be set independently from the state of TXRTSE an...

Страница 1455: ...ase 10h offset 4006_A010h UART1_PFIFO is 4006_B000h base 10h offset 4006_B010h UART2_PFIFO is 4006_C000h base 10h offset 4006_C010h UART3_PFIFO is 4006_D000h base 10h offset 4006_D010h UART4_PFIFO is...

Страница 1456: ...atawords 110 Transmit FIFO Buffer Depth 128 Datawords 111 Reserved 3 RXFE Receive FIFO Enable When this bit is set the built in FIFO structure for the receive buffer is enabled The size of the FIFO st...

Страница 1457: ...lush Writing to this bit causes all data that is stored in the transmit FIFO buffer to be flushed This does not affect data that is in the transmit shift register 0 No flush operation occurs 1 All dat...

Страница 1458: ...d Description 7 TXEMPT Transmit Buffer FIFO Empty This status bit asserts when there is no data in the Transmit FIFO buffer This bit does not take into account data that is in the transmit shift regis...

Страница 1459: ...hould only be written when C2 TE is not set Changing the value of the watermark will not clear the S1 TDRE flag Addresses UART0_TWFIFO is 4006_A000h base 13h offset 4006_A013h UART1_TWFIFO is 4006_B00...

Страница 1460: ...ft register it is not included in the count This value may be used in conjunction with the PFIFO TXFIFOSIZE field to calculate how much room is left in the transmit buffer FIFO 52 3 21 UART FIFO Recei...

Страница 1461: ..._A000h base 16h offset 4006_A016h UART1_RCFIFO is 4006_B000h base 16h offset 4006_B016h UART2_RCFIFO is 4006_C000h base 16h offset 4006_C016h UART3_RCFIFO is 4006_D000h base 16h offset 4006_D016h UART...

Страница 1462: ...nse if a receive buffer overrun occurs as indicated by the S1 OR field In many systems this will result in the transmitter resending the packet that overflowed until the retransmit threshold for that...

Страница 1463: ...816E ISO 7816 Functionality Enabled This bit indicates that the UART is operating according to the ISO 7816 protocol NOTE This bit should only be modified when no transmit or receive is occurring If t...

Страница 1464: ...ill not result in the generation of an interrupt 1 The assertion of the IS7816 INITD bit will result in the generation of an interrupt 3 Reserved This read only field is reserved and always has the va...

Страница 1465: ...d WT CWT BWT INITD 0 GTV TXT RXT Write Reset 0 0 0 0 0 0 0 0 UARTx_IS7816 field descriptions Field Description 7 WT Wait Timer Interrupt This flag indicates that the wait time the time between the lea...

Страница 1466: ...is cleared and the count restarts from zero on the next received NACK This interrupt is cleared by writing 1 0 The number of retries and corresponding NACKS does not exceed the value in the ET7816 TX...

Страница 1467: ...e 1Bh offset 4006_C01Bh UART3_WP7816T0 is 4006_D000h base 1Bh offset 4006_D01Bh UART4_WP7816T0 is 400E_A000h base 1Bh offset 400E_A01Bh UART5_WP7816T0 is 400E_B000h base 1Bh offset 400E_B01Bh Bit 7 6...

Страница 1468: ...6T1 is 400E_A000h base 1Bh offset 400E_A01Bh UART5_WP7816T1 is 400E_B000h base 1Bh offset 400E_B01Bh Bit 7 6 5 4 3 2 1 0 Read CWI BWI Write Reset 0 0 0 0 1 0 1 0 UARTx_WP7816T1 field descriptions Fiel...

Страница 1469: ...eter used in the calculation of GT CGT and BGT counters The value represents an integer number 0 255 See Wait time and guard time parameters 52 3 29 UART 7816 Wait FD Register UARTx_WF7816 The WF7816...

Страница 1470: ...st processor is notified Meaning a value of 0 will always result in TXT asserting on the first NACK that is received A value of 1 will result in TXT being asserted on the second NACK that is received...

Страница 1471: ...n of the block Additionally this register is automatically decremented by 1 for the first character of a CRC in the epilogue field Hence this register should be programmed with the number of bytes in...

Страница 1472: ...IC TxD IRQ DMA LOGIC INFRARED LOGIC DMA Requests IRQ Requests TxD LOOP CONTROL LOOPS RSRC UART DATA REGISTER UART_D Figure 52 218 Transmitter Block Diagram 52 4 1 1 Transmitter character length The UA...

Страница 1473: ...s to the transmit buffer using C3 T8 D as space permits See Application information for specific programing sequences Setting the C2 TE bit automatically loads the transmit shift register with a pream...

Страница 1474: ...he FIFO is transmitted on the link before clearing C2 TE wait for the S1 TC flag to set Alternatively the same can be achieved by setting TWFIFO TXWATER to 0x0 and waiting for S1 TDRE to set 52 4 1 4...

Страница 1475: ...setting the C2 TE bit during a transmission queues an idle character to be sent after the dataword currently being transmitted Note When queuing an idle character the idle character will be transmitte...

Страница 1476: ...ins asserted for the whole time that the transmitter data buffer has any characters RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sen...

Страница 1477: ...a buffer write CTS_B RTS_B C1 in transmission 1 1 Cn transmit characters Figure 52 219 Transmitter RTS and CTS timing diagram Chapter 52 Universal Asynchronous Receiver Transmitter UART K53 Sub Family...

Страница 1478: ...ver character length The UART receiver can accommodate 8 9 or 10 bit data characters The states of the C1 M and C1 PE bits and the C4 M10 bit determine the length of data characters When receiving 9 o...

Страница 1479: ...perates slightly differently Upon receipt of the parity bit the validity of the parity bit is checked If C7816 ANACK is set and the parity check fails or if INIT and the received character is not a va...

Страница 1480: ...4 RT15 RT16 1 1 1 1 0 0 0 0 0 0 RT10 RT12 RT1 START BIT QUALIFICATION DATA SAMPLING START BIT VERIFICATION Figure 52 221 Receiver data sampling To verify the start bit and to detect noise data recover...

Страница 1481: ...s set enabled where the values of RT8 RT9 and RT10 exclusively determine if a start bit exists To verify a stop bit and to detect noise recovery logic takes samples at RT8 RT9 and RT10 The following t...

Страница 1482: ...s the noise flag Although the perceived bit time is misaligned the data samples RT8 RT9 and RT10 are within the bit time and data recovery is successful SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RE...

Страница 1483: ...T CLOCK 1 1 1 1 0 PERCEIVED AND ACTUAL START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT2 RT3 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 1 1 1 1 1 1 0 Figure 52 225...

Страница 1484: ...igh SAMPLES Rx pin input RT CLOCK RT CLOCK COUNT RESET RT CLOCK 1 1 1 1 0 0 START BIT LSB RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT10 RT1 RT2 RT3 1 1 1 1 1 0 0 1 0 1 RT4 RT5 RT6 RT7 RT8 RT9 R...

Страница 1485: ...in a LIN system by setting the S2 LBKDE bit The UART break character detection threshold depends on the C1 M and C1 PE bits the C4 LBKDE bit and the C4 M10 bit Refer to the following table Table 52 2...

Страница 1486: ...easserted the receiver continues to receive characters until the receiver data buffer is full or is overrun If the receiver request to send functionality is disabled the receiver RTS remains deasserte...

Страница 1487: ...er counter also is reset 52 4 2 8 4 High bit detection At 16 RT clocks after the previous rising edge if a rising edge is not seen then the decoder sends a 1 to the receiver If the next bit is a 0 whi...

Страница 1488: ...les 10 RT cycles With the misaligned character shown in the above figure the receiver counts 154 RT cycles at the point when the count of the transmitting device is 147 RT cycles 9 bit times 16 RT cyc...

Страница 1489: ...cter with no errors is 154 160 154 100 3 90 For a 9 bit data character data sampling of the stop bit takes the receiver 170 RT cycles 10 bit times 16 RT cycles 10 RT cycles With the misaligned charact...

Страница 1490: ...816 ISO_7816E is set enabled 52 4 2 10 2 Address mark wakeup C1 WAKE 1 In this wakeup method a logic 1 in the bit position immediately preceding the stop bit of a frame clears the C2 RWU bit and wakes...

Страница 1491: ...ansferred to the receive data buffer only on a match If C4 MAEN1 and C4 MAEN2 are asserted a marked address is compared with both match registers and data is transferred only on a match with either re...

Страница 1492: ...9 04 19 200 0 047 66 00000 0 154 545 5 9659 1 9600 0 62 133 00000 0 76 691 7 4793 2 4800 0 14 266 00000 0 38 345 9 2396 6 2400 0 14 531 00000 0 19 209 0 1200 6 1200 0 11 1062 00000 0 9604 5 600 3 600...

Страница 1493: ...udes a start bit and a stop bit The rest of the data format depends upon UARTx_C1 M UARTx_C1 PE UARTx_S2 MSBF and UARTx_C4 M10 52 4 4 1 Eight bit configuration Clearing the UART_C1 M configures the UA...

Страница 1494: ...bit is being used as an address mark When UARTx_C1 M is set and UARTx_C4 M10 is set the UART is configured for 9 bit data characters but the frame consists of a total of 12 bits The 12 bits include t...

Страница 1495: ...231 Eight bits of data with LSB first BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STOP BIT ADDRESS MARK START BIT START BIT Figure 52 232 Eight bits of data with MSB first 52 4 4 3 2 Eight bit fo...

Страница 1496: ...BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 PARITY STOP BIT START BIT START BIT BIT 0 ADDRESS MARK Figure 52 239 Nine bits of data with LSB first and parity BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PA...

Страница 1497: ...er Clearing the C1 RSRC bit connects the transmitter output to the receiver input Both the transmitter and receiver must be enabled C2 TE 1 and C2 RE 1 When C7816 ISO_7816EN is set it is not a require...

Страница 1498: ...ent those options being used Further the UART may provide configuration options that exceed the flexibility of options explicitly allowed by the 7816 specification Failure to correctly configure the U...

Страница 1499: ...stop bits rather than the typical single stop bit In addition to a standard even parity check the receiver has the ability to generate and return a NACK during the second half of the first stop bit pe...

Страница 1500: ...of the epilogue 52 4 7 4 Wait time and guard time parameters The ISO 7816 specification defines several wait time and guard time parameters The UART allows for flexible configuration and violation det...

Страница 1501: ...er The UART will automatically handle GT CGT and BGT such that the UART will not send a packet prior to the corresponding guard time expiring Table 52 237 Wait and guard time calculations Parameter Re...

Страница 1502: ...o diode and transformed to CMOS levels by the IR receive decoder external from the MCU The narrow pulses are then stretched by the infrared receive decoder to get back to a serial bit stream to be rec...

Страница 1503: ...ART The local enables for the UART interrupt sources are described in this table Details regarding the individual operation of each interrupt are contained under various sub sections of Memory map and...

Страница 1504: ...2 RXINV is programmed to zero and to detect rising edge S2 RXINV is programmed to one Synchronizing logic is used prior to detect edges Prior to detecting an edge the receive data on RxD input must be...

Страница 1505: ...e clearing mechanism of reading S1 register followed by reading D register does not clear the associated flag The DMA request remains asserted until an indication is received that the DMA transactions...

Страница 1506: ...w to program the UART for ISO 7816 operation Elements such as procedures to power up or power down the smartcard and when to take those actions are beyond the scope of this description To setup the UA...

Страница 1507: ...d then adjust 7816 specific and UART generic parameters to match and configuration data that was received during the answer on reset period Once the new settings have been programmed including the new...

Страница 1508: ...ncy to ensure that the block wait time and character wait times are not violated 52 8 3 Initialization sequence non ISO 7816 To initiate an UART transmission 1 Configure the UART a Select a baud rate...

Страница 1509: ...it 4 Write the first and subsequent datawords of the second message to C3 T8 D 52 8 4 Overrun OR flag implications To be flexible the overrun flag OR operates slight differently depending on the mode...

Страница 1510: ...the lost data may be resent and hence recoverable When LIN break detect LBKDE is asserted the S1 OR flag has significantly different behavior than in other modes The S1 OR bit will be set regardless...

Страница 1511: ...an example 52 8 7 Modem feature This section describes the modem features 52 8 7 1 Ready to receive using RTS To help to stop overrun of the receiver data buffer the RTS signal can be used by the rece...

Страница 1512: ...The IrDA specifies a minimum pulse width of 1 6 s The UART hardware does not include a mechanism to restrict force the pulse width to be greater than or equal to 1 6 s However configuring the baud rat...

Страница 1513: ...are not listed here may also need to be considered 1 Various reserved registers and register bits were used i e MSFB and M10 2 This module now generates an error when invalid address spaces are used...

Страница 1514: ...Application information K53 Sub Family Reference Manual Rev 6 Nov 2011 1514 Freescale Semiconductor Inc...

Страница 1515: ...ith a single data pin while the new high speed MMC communication is based on an advanced 11 pin serial bus designed to operate in the low voltage range The secure digital card SD is an evolution of th...

Страница 1516: ...st Controller Peripheral bus SD card SDIO card Figure 53 1 System connection of the SDHC CE ATA is a hard drive interface that is optimized for embedded applications storage The device is layered on t...

Страница 1517: ...h master port DMA request Figure 53 2 Enhanced secure digital host controller block diagram 53 2 3 Features The features of the SDHC module include the following Conforms to the SD Host Controller Sta...

Страница 1518: ...rts both synchronous and asynchronous abort both hardware and software CMD12 Supports pause during the data transfer at block gap Supports SDIO read wait and suspend resume operations Supports auto CM...

Страница 1519: ...nses from the card I O SDHC_D0 DAT0 line or busy state detect I O SDHC_D1 8 bit mode DAT1 line 4 bit mode DAT1 line or interrupt detect 1 bit mode Interrupt detect I O SDHC_D2 4 8 bit mode DAT2 line o...

Страница 1520: ...0000h 53 4 3 1523 400B_100C Transfer Type Register SDHC_XFERTYP 32 R W 0000_0000h 53 4 4 1524 400B_1010 Command Response 0 SDHC_CMDRSP0 32 R 0000_0000h 53 4 5 1528 400B_1014 Command Response 1 SDHC_CM...

Страница 1521: ...S 32 R 0000_0000h 53 4 20 1562 400B_1058 ADMA System Address Register SDHC_ADSADDR 32 R W 0000_0000h 53 4 21 1564 400B_10C0 Vendor Specific Register SDHC_VENDOR 32 R W 0000_0001h 53 4 22 1564 400B_10C...

Страница 1522: ...ata blocks and the number of bytes in each block Address SDHC_BLKATTR is 400B_1000h base 4h offset 400B_1004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Страница 1523: ...from 1 byte up to the maximum buffer size can be set It can be accessed only when no transaction is executing that is after a transaction has stopped Read operations during transfers may return an in...

Страница 1524: ...5 of this register is 0 when written or block count is disabled bit 1 of this register is 0 when written otherwise SDHC will ignore the sending of this command and do nothing For write command with al...

Страница 1525: ...heck enable CICEN CRC check enable CCCEN Name of response type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3 R4 10 1 1 R1 R5 R6 11 1 1 R1b R5b NOTE In the SDIO specification response type notation for R5b i...

Страница 1526: ...tatus of the suspend command and send another command marked as suspend to inform the SDHC that a suspend command was successfully issued After the end bit of command is sent the SDHC de asserts read...

Страница 1527: ...mand CRC Check Enable If this bit is set to 1 the SDHC shall check the CRC field in the response If an error is detected it is reported as a Command CRC Error If this bit is set to 0 the CRC field is...

Страница 1528: ...gister which is only relevant for multiple block transfers When this bit is 0 the internal counter for block is disabled which is useful in executing an infinite transfer 0b Disable 1b Enable 0 DMAEN...

Страница 1529: ...2 is 400B_1000h base 18h offset 400B_1018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CMDRSP2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1530: ...e host driver to efficiently read 32 bit of response data in one read cycle on a 32 bit bus system Parts of the response the index field and the CRC are checked by the SDHC as specified by the XFERTYP...

Страница 1531: ...data access by the CPU or the external DMA When the internal DMA is enabled any write to this register is ignored and any read from this register will always yield 0s 53 4 10 Present State Register S...

Страница 1532: ...Data 3 line signal level DAT 4 Data 4 line signal level DAT 5 Data 5 line signal level DAT 6 Data 6 line signal level DAT 7 Data 7 line signal level 23 CLSL CMD Line Signal Level This status is used t...

Страница 1533: ...than the write watermark level 9 RTA Read Transfer Active This status bit is used for detecting completion of a read transfer This bit is set for either of the following conditions After the end bit o...

Страница 1534: ...Internally This status bit indicates that the SDHC clock is internally gated off This bit is for the host driver to debug transaction on the SD bus When INITA bit is set SDHC sending 80 clock cycles t...

Страница 1535: ...read wait signal is already driven data buffer cannot receive data the SDHC can wait for a current block gap by continuing to drive the read wait signal It is necessary to support read wait in order...

Страница 1536: ...ommand conflict error Refer to command CRC error or because of a command not issued by auto CMD12 error this bit will remain 1 and the command complete is not set The status of issuing an auto CMD12 d...

Страница 1537: ...SD Card Insertion This bit enables a wakeup event via IRQSTAT CINS FN_WUS Wake Up Support in CIS does not effect this bit When this bit is set the IRQSTATEN CINSEN and the SDHC interrupt can be assert...

Страница 1538: ...is bit to restart the paused transfer To cancel stop at the block gap set PROCTL SABGREQ to 0 and set this bit to 1 to restart the transfer The SDHC automatically clears this bit therefore it is not n...

Страница 1539: ...n Pin If this bit is set DAT3 should be pulled down to act as a card detection pin Be cautious when using this feature because DAT3 is also a chip select for the SPI mode A pulldown on this pin and CM...

Страница 1540: ...wer up period when 74 SD clocks are needed and the clock auto gating feature is enabled Writing 1 to this bit when this bit is already 1 has no effect Writing 0 to this bit at any time has no effect W...

Страница 1541: ...all does not affect the value of the capabilities registers After this bit is set it is recommended that the host driver reset the external card and re initialize it 0b No reset 1b Reset 23 20 Reserv...

Страница 1542: ...ed by 64 40h Base clock divided by 128 80h Base clock divided by 256 7 4 DVS Divisor This register is used to provide a more exact divisor to generate the desired SD clock frequency Note the divider c...

Страница 1543: ...to send or Clock divisor is just updated or Continue request is just set or This bit is set or Card insertion is detected or Card removal is detected or Card external interrupt is detected or The SDH...

Страница 1544: ...meout error transfer complete bit combinations Transfer complete Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during transfer 1 X Data transfer complete The table below shows th...

Страница 1545: ...or corrupts the whole data block the host driver shall re start the transfer from the corrupted block boundary The address of the block boundary can be calculated either from the current DSADDR value...

Страница 1546: ...ed and the Command Timeout Error is set to 0 indicating no time out this bit is set when detecting a CRC error in the command response The SDHC detects a CMD line conflict by monitoring the CMD line w...

Страница 1547: ...1 to clear this status the status of the Card Inserted in the Present State register should be confirmed Because the card state may possibly be changed when the host driver clears this bit and the int...

Страница 1548: ...er is completed In the case of a read transaction This bit is set at the falling edge of the read transfer active status There are two cases in which this interrupt is generated The first is when a da...

Страница 1549: ...river must set both IRQSTATEN CTOESEN and IRQSTATEN CCESEN to 1 Address SDHC_IRQSTATEN is 400B_1000h base 34h offset 400B_1034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 DMAESEN 0 AC12ES...

Страница 1550: ...Enabled 16 CTOESEN Command Timeout Error Status Enable 0b Masked 1b Enabled 15 9 Reserved This read only field is reserved and always has the value zero 8 CINTSEN Card Interrupt Status Enable If this...

Страница 1551: ...er Write Ready Status Enable 0b Masked 1b Enabled 3 DINTSEN DMA Interrupt Status Enable 0b Masked 1b Enabled 2 BGESEN Block Gap Event Status Enable 0b Masked 1b Enabled 1 TCSEN Transfer Complete Statu...

Страница 1552: ...0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CINTIEN CRMIEN CINSIEN BRRIEN BWRIEN DINTIEN BGEIEN TCIEN CCIEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDHC_IRQSIGEN field descriptions Field Descr...

Страница 1553: ...ble 0b Masked 1b Enabled 15 9 Reserved This read only field is reserved and always has the value zero 8 CINTIEN Card Interrupt Enable 0b Masked 1b Enabled 7 CRMIEN Card Removal Interrupt Enable 0b Mas...

Страница 1554: ...table shows the relationship between the Auto CMGD12 CRC error and the Auto CMD12 command timeout error Table 53 25 Relationship Between Command CRC Error and Command Timeout Error for Auto CMD12 Aut...

Страница 1555: ...set An Auto CMD12 error interrupt is generated when one of the error bits 0 4 is set to 1 The command not issued by auto CMD12 error does not generate an interrupt Address SDHC_AC12ERR is 400B_1000h b...

Страница 1556: ...curs when detecting that the end bit of command response is 0 which should be 1 0b No error 1b End bit error generated 1 AC12TOE Auto CMD12 Timeout Error Occurs if no response is returned within 64 SD...

Страница 1557: ...4 3 2 1 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDHC_HTCAPBLT field descriptions Field Description 31 27 Reserved This read only field is reserved and always has the value zero 26 VS18 Voltage...

Страница 1558: ...HC supports high speed mode and the host system can supply a SD Clock frequency from 25 MHz to 50 MHz 0b High speed not supported 1b High speed supported 20 ADMAS ADMA Support This bit indicates wheth...

Страница 1559: ...15 13 Reserved This read only field is reserved and always has the value zero 12 8 Reserved This read only field is reserved and always has the value zero 7 0 RDWML Read Watermark Level The number of...

Страница 1560: ...eld descriptions Field Description 31 CINT Force Event Card Interrupt Writing 1 to this bit generates a short low level pulse on the internal DAT 1 line as if a self clearing interrupt was received fr...

Страница 1561: ...eserved This field is reserved 7 CNIBAC12E Force Event Command Not Executed By Auto Command 12 Error Forces the AC12ERR CNIBAC12E bit to be set 6 5 Reserved This field is reserved 4 AC12IE Force Event...

Страница 1562: ...descriptor address In case of a write operation the host driver should use the ACMD22 to get the number of the written block rather than using this information since unwritten data may exist in the h...

Страница 1563: ...scriptor is fetched by ADMA 0b No error 1b Error 2 ADMALME ADMA Length Mismatch Error This error occurs in the following 2 cases While the block count enable is being set the total data length specifi...

Страница 1564: ...ecutable descriptor command When the ADMA error interrupt is generated this register shall hold the valid descriptor address depending on the ADMA state The lower 2 bits of this register is tied to 0...

Страница 1565: ...act block number This bit must not be set if the CMD53 multi block read is not exact block number 0 none exact block read 1 Exact block read for SDIO CMD53 0 EXTDMAEN External DMA Request Enable Enabl...

Страница 1566: ...ck cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1 then stop at block gap 15 8 Reserved This read only field is reserved and always has the value zero 7 AUTOSABGEN When boot enable auto stop at block g...

Страница 1567: ...0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 SDHC_HOSTVER field descriptions Field Description 31 16 Reserved This read only field is reserved and always has the value zero 15 8 VVN Vendor Version Number The...

Страница 1568: ...system and the card The watermark levels for read and write are both configurable and can be any number from 1 to 128 words The burst lengths for read and write are also configurable and can be any n...

Страница 1569: ...ever be sent out For a read operation when there are more words in the buffer than the amount set in the WML register the internal DMA starts fetching data over the crossbar switch bus Except INCR4 an...

Страница 1570: ...alue set in the WML register and is ready for receiving new data At the same time the SDHC would set the IRQSTAT BWR bit The buffer write ready interrupt will be generated if it is enabled by software...

Страница 1571: ...C will abort the data transfer and abandon the current block The host driver should read the content of the DMA system address register to get the starting address of the abandoned data block If the c...

Страница 1572: ...beats of write access in total 53 5 1 4 Dividing large data transfer This SDIO command CMD53 definition limits the maximum data size of data transfers according to the following formula Max data size...

Страница 1573: ...ber of WRWML words can be held in the buffer free space a DMA request is sent informing the host system of a DMA write The IRQSTAT BWR bit is also set as long as the IRQSTATEN BWRSEN bit is set The DM...

Страница 1574: ...to any number of word For this case the BLKATTR BLKSIZE bits shall be set as 1fh For the CPU polling access the burst length can be 1 to 128 words without restriction This is because the software will...

Страница 1575: ...sent The data transfer is in the block unit and the subsequent watermark level is always set as the remaining number of words For instance for a multi block data read with each block size of 31 bytes...

Страница 1576: ...d For simple DMA once the page boundary is reached a DMA interrupt will be generated and the new system address shall be programmed by the host driver The ADMA defines the programmable descriptor tabl...

Страница 1577: ...rom most recent descriptor s For ADMA1 the valid data length descriptor is the last set type descriptor before tran type descriptor Every tran type will trigger a transfer and the transfer data length...

Страница 1578: ...Length invisible Flags Flags State Machine Data Address invisible Address Length Attribute Tran Link Address Address Address Address Length Data Length Address Address Attribute Set Tran End Descripto...

Страница 1579: ...33 Concept and access method of ADMA2 descriptor table 53 5 2 4 2 ADMA interrupt If the interrupt flag of descriptor is set ADMA will generate an interrupt according to different type descriptor For A...

Страница 1580: ...f block length otherwise when all data set in the descriptor nodes are done not at block boundary the data mismatch error will occur 53 5 3 SD protocol unit The SD protocol unit deals with all SD prot...

Страница 1581: ...he WP write protect line With the information of the WP state the register bank will ignore the command accompanied by a write operation when the WP switch is on If the internal data buffer is in dang...

Страница 1582: ...r The CRC polynomials for the DAT are as follows Generator polynomial G x x16 x12 x5 1 M x first bit xn second bit xn 1 last bit x0 CRC 15 0 Remainder M x x16 G x 53 5 4 Clock reset manager This modul...

Страница 1583: ...riving clock for all sub modules of the SD protocol unit and the sync FIFOs to synchronize with the data rate from the internal data buffer The frequency of the clock output from this stage can be DIV...

Страница 1584: ...if an interrupt is pending the SDHC_D1 line will be held low for one clock cycle with the last clock cycle pulling SDHC_D1 high On completion of the Interrupt Period the card releases the SDHC_D1 lin...

Страница 1585: ...to CPU IP Bus eSDHC Registers IRQ Detecting Steering SD Host SDIO Card SDIO Card IRQ Routing IRQ0 IRQ1 Function 0 Function 1 Clear IRQ0 Clear IRQ1 Enable card IRQ in Host Start No Yes Figure 53 36 Car...

Страница 1586: ...hich can be used as wake up events are 1 Card removal interrupt 2 Card insertion interrupt 3 Interrupt from SDIO card The SDHC offers a power management feature By clearing the clock enabled bits in t...

Страница 1587: ...5 9 1 Boot operation Note in this block guide this fast boot is called normal fast boot mode If the CMD line is held low for 74 clock cycles and more after power up before the first command is issued...

Страница 1588: ...fter 74 clock cycles before CMD1is issued or the CMD line goes low the slave recognizes that boot mode is being initiated and starts preparing boot data internally Within 1 second after CMD0 with the...

Страница 1589: ...ter standby mode Addressed type commands are used from this point In this mode the CMD DAT I O pads will turn to push pull mode to have the driving capability for maximum frequency operation Refer to...

Страница 1590: ...For some scenarios the response time out is expected For instance after all cards respond to CMD3 and go to the standby state no response to the host when CMD2 is sent The host driver shall deal with...

Страница 1591: ...60 to check for a CE ATA signature If the device responds to the command with the CE ATA signature a CE ATA device has been found Then the driver should query EXT_CSD register byte 504 S_CMD_SET in t...

Страница 1592: ...For CE ATA device that supports ATA mode before issuing CMD0 to reset the MMC layer two CMD39 should be issued back to back to the ATA control register The first CMD39 shall have the SRST bit set to o...

Страница 1593: ...e range before sending out of range cards into the inactive state This query should be used if the host is able to select a common voltage range or if a notification shall be sent to the system when a...

Страница 1594: ...is activated the host will request the card to send their valid operation conditions The response to ACMD41 is the operation condition register of the card The same command shall be send to all of the...

Страница 1595: ...to the card a relative card address RCA Once the RCA is received the card state changes to the standby state and the card does not react in further identification cycles and its output driver switche...

Страница 1596: ...e CID and CSD registers does not require a previous block length setting The transferred data is also CRC protected If a part of the CSD or CID register is stored in ROM then this unchangeable part mu...

Страница 1597: ...stance 5 Disable the buffer write ready interrupt configure the DMA settings and enable the eSDHC DMA when sending the command with data transfer The AC12EN bit should also be set 6 Wait for the Trans...

Страница 1598: ...it to continue the write operation 11 Wait for the transfer complete interrupt 12 Check the status bit to see if a write CRC error occurred or some another error that occurred during the auto12 comman...

Страница 1599: ...rd specification A CRC is appended to the end of each block ensuring data transfer integrity The CMD17 CMD18 CMD53 CMD60 CMD61 and so on can initiate a block read After completing the transfer the car...

Страница 1600: ...er to pause the transfer between the data blocks Before setting the SABGREQ bit make sure the RWCTL bit in the Protocol Control register is set otherwise the eSDHC will not assert the Read Wait signal...

Страница 1601: ...mand read operation Unlike the write operation there is no remaining data inside the buffer when the transfer is paused All data received before the pause will be transferred to the Host System No mat...

Страница 1602: ...step until the BS bit is cleared or abandon the suspend operation according to the Driver strategy 4 Send another normal I O command to the suspended function The XFERTYP CMDTYP of this command must...

Страница 1603: ...PROCTL DMAS field to 01 to select the ADMA 7 Issue a write or read command with the XFERTYP DMAEN bit set to 1 Steps 1 5 are independent of step 6 so step 6 can finish before steps 1 5 Regarding the...

Страница 1604: ...transfer the start address of transfer and the size of each block the start address of corrupted block can be determined When the BCEN bit is not set the contents of the block attribute register does...

Страница 1605: ...with this command occur it is recommended to the driver to deal with the situations in the following manner 1 Auto CMD12 response time out It is not certain whether the command is accepted by the car...

Страница 1606: ...by a CMD6 with the mnemonic symbol as SWITCH The 4 bit and 8 bit bus width of the MMC is also enabled by the SWITCH command but with a different argument These new functions can also be disabled by a...

Страница 1607: ...xF report the function switch failed and return change clock divisor value or configure the system clock feeding into eSDHC to generate the card_clk of the desired value below 25MHz data transactions...

Страница 1608: ...tions like normal peers 53 6 5 ADMA operation This section presents code examples for ADMA operation 53 6 5 1 ADMA1 operation Set_adma1_descriptor if to start data transfer Make sure the address is 4K...

Страница 1609: ...53 6 6 Fast boot operation This section discusses fast boot operations 53 6 6 1 Normal fast boot flow 1 Software need to configure SYSCTL INITA to make sure 74 card clocks are finished 2 Software need...

Страница 1610: ...t This will make CMD line high and command completed asserted After at least 56 clocks it is ready to begin normal initialization process 9 Reset the host and then can begin the normal process 53 6 6...

Страница 1611: ...ation step 9 Reset the host and then can begin the normal process 53 6 6 3 Fast boot application case in DMA mode In the boot application case because the image destination and the image size are cont...

Страница 1612: ...t is set to 1 XFERTYP DTDSEL is set to 1 XFERTYP MSBSEL is set to 1 XFERTYP DMAEN is configured as 1 in DMA mode And if XFERTYP BCEN is configured as 1 better to configure blk no in BLKATTR register t...

Страница 1613: ...ng it is the useful data so software need to deal the data due to the application case 53 6 7 Commands for MMC SD SDIO CE ATA The following table lists the commands for the MMC SD SDIO CE ATA cards Re...

Страница 1614: ...unction 30 8 Reserved for function groups 6 3 All 0 or 0xFFFF 7 4 Function group1 for command system 3 0 Function group2 for access mode R1 SWITCH_FUNC Checks switch ability mode 0 and switch card fun...

Страница 1615: ...RCA 15 0 stuff bits GO_INACTIVE_STAT E Sets the card to inactive state in order to protect the card stack against communication breakdowns CMD16 ac 31 0 block length R1 SET_BLOCKLEN Sets the block le...

Страница 1616: ...RP_SIZE CMD29 ac 31 0 data address R1b CLR_WRITE_PROT If the card provides write protection features this command clears the write protection bit of the addressed group CMD30 adtc 31 0 write protect d...

Страница 1617: ...sses application dependent registers which are not defined in the MMC standard CMD40 bcr 31 0 stuff bits R5 GO_IRQ_STATE Sets the system into interrupt mode CMD41 Reserved CDM42 adtc 31 0 stuff bits R...

Страница 1618: ...used to read and write these registers CMD61 adtc 31 WR 30 16 stuff bits 15 0 data unit count R1b RW_MULTIPLE_BLOC K The host issues a RW_MULTIPLE_BLOCK CMD61 to begin the data transfer for the ATA co...

Страница 1619: ...ed with the APP_CMD command Commands listed are used for SD only other SD commands not listed are not supported on this module 7 ACMDs shall be preceded with the APP_CMD command Commands listed are us...

Страница 1620: ...2 then the access times for the burst sequence in the whole transfer process must be 4 4 2 4 4 2 53 7 3 Suspend operation In order to suspend the data transfer the software must inform SDHC that the s...

Страница 1621: ...automatically gates off the card clock when the host driver changes the clock frequency To remove possible glitch on the card clock clear SYSCTL SDCLKEN bit when changing clock divisor value and set S...

Страница 1622: ...Software restrictions K53 Sub Family Reference Manual Rev 6 Nov 2011 1622 Freescale Semiconductor Inc...

Страница 1623: ...ex serial port that allows the chip to communicate with a variety of serial devices Such serial devices are Standard codecs Digital signal processors DSPs Microprocessors Peripherals Audio codecs that...

Страница 1624: ...SYS_CLK SRFS Tx Clock Generator Tx Sync Generator Tx and RX Rx Clock Generator Rx Sync Generator Control Reg CR Tx and Rx FIFO and shift register logic Control TCR TCCR 32 bit RCCR Receive Clock Cont...

Страница 1625: ...from SRCK in I2S master mode AC97 support Completely separate clock and frame sync selections for the receive and transmit sections In the AC97 standard the clock is taken from an external source and...

Страница 1626: ...g of slots for transmit and receive section can differ in synchronous mode Also the RCR RXBIT0 RSHFD bits can continue affecting shifting in of received data in synchronous mode In asynchronous mode t...

Страница 1627: ...h require some specific programming I2S mode AC97 mode AC97 fixed mode AC97 variable mode In non I2S slave modes external frame sync the I2S s programmed word length setting should be equal to the wor...

Страница 1628: ...sync is used by the transmitter to synchronize the transfer of data The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfe...

Страница 1629: ...RFDIR 1 TCR TFDIR 0 CR SYN 0 I2S external continuous clock for TX I2S internal continuous clock for TX RCR RXDIR 0 TCR TXDIR 1 RCR RFDIR 0 TCR TFDIR 1 CR SYN 0 I2S external continuous clock for RX Fi...

Страница 1630: ...0 0 0 0 RCK in TCK in RFS in TFS in 0 0 0 0 1 RCK in TCK in RFS in TFS out 0 0 1 0 0 RCK in TCK in RFS out TFS in 0 0 1 0 1 RCK in TCK in RFS out TFS out 0 0 0 1 0 RCK in TCK out RFS in TFS in 0 0 0 1...

Страница 1631: ...mber Details of register bit and field function follow the register diagrams in bit order I2S memory map Absolute address hex Register name Width in bits Access Reset value Section page 4002_F000 I2S...

Страница 1632: ...0_ACNT 32 R W 0000_0000h 54 3 13 1660 4002_F03C I2S AC97 Command Address Register I2S0_ACADD 32 R W 0000_0000h 54 3 14 1661 4002_F040 I2S AC97 Command Data Register I2S0_ACDAT 32 R W 0000_0000h 54 3 1...

Страница 1633: ...16 is discarded Example If Tx FIFO0 is not in use and you write Data1 Data2 to TX0 then Data2 does not overwrite Data1 and is discarded NOTE Enable I2S CR I2SEN 1 before writing to the I2S transmit da...

Страница 1634: ...the data received by the I2S These are implemented as the first word of their respective Rx FIFOs These bits receive data from the RXSR depending on the mode of operation In case both FIFOs are in use...

Страница 1635: ...e zero 12 SYNCTXFS SYNCTXFS bit provides a safe window for CR TE to be visible to the internal circuit which is just after FS occurrence When SYNCTXFS is set CR TE gets latched on FS occurrence and la...

Страница 1636: ...during I2S internal gated mode Note When Clock idle state is 1 the clock polarity should always be negedge triggered and when clock idle 0 the clock polarity should always be positive edge triggered...

Страница 1637: ...boundary is detected When this bit is cleared the transmitter continues to send data until the end of the current frame and then stops Data can be written to the TX registers with the CR TE bit clear...

Страница 1638: ...AISR register are not generated The status bits are described in the following table NOTE I2S status flags are valid when I2S is enabled All the flags in the ISR are updated after the first bit of the...

Страница 1639: ...TFRCLKDIS when transmitter is already disabled 22 19 Reserved This read only field is reserved and always has the value zero 18 CMDAU Command Address Register Updated This bit causes the command addre...

Страница 1640: ...when the core writes to TX1 If IER TIE and IER TDE1EN are set an I2S transmit data 1 interrupt request is issued on setting of TDE1 bit The TDE1 bit is cleared by POR and I2S reset 0 Data available fo...

Страница 1641: ...ires data transmission unless masked through TMSK register when the transmitter is enabled CR TE is set The TUE0 flag causes an interrupt if IER TIE and IER TUE0EN are set The TUE0 bit is cleared by P...

Страница 1642: ...automatically cleared when the amount of data in Rx FIFO1 falls below the threshold The RFF1 bit is cleared by POR and I2S reset When Rx FIFO1 contains 15 words the maximum it can hold all further da...

Страница 1643: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 RFRC_EN TFRC_EN RDMAE RIE TDMAE TIE CMDAUEN CMDDUEN RXTEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RDR1E...

Страница 1644: ...MA request is generated when the corresponding TDE bit is set 0 I2S transmitter DMA requests disabled 1 I2S transmitter DMA requests enabled 19 TIE Transmit Interrupt Enable This control bit allows th...

Страница 1645: ...Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not 0 Corresponding status bit cannot issue interrupt 1 Corresponding status bit can issue interrup...

Страница 1646: ...nterrupt 3 RFF1EN Enable Bit Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not 0 Corresponding status bit cannot issue interrupt 1 Corresponding s...

Страница 1647: ...FIFO Enable 1 This bit enables transmit FIFO 1 When enabled the FIFO allows 15 samples to be transmitted by the I2S per channel a 9th sample can be shifting out before TDE1 bit is set When the FIFO i...

Страница 1648: ...edge of bit clock 2 TFSI Transmit Frame Sync Invert This bit controls the active state of the frame sync I O signal for the transmit section of I2S 0 Transmit frame sync is active high 1 Transmit fram...

Страница 1649: ...can be MSB or LSB first controlled by the RSHFD bit 0 Shifting with respect to bit 31 if word length 16 18 20 22 or 24 or bit 15 if word length 8 10 or 12 of receive shift register MSB aligned 1 Shift...

Страница 1650: ...ty This bit controls which bit clock edge is used to latch in data for the receive section 0 Data latched on falling edge of bit clock 1 Data latched on rising edge of bit clock 2 RFSI Receive Frame S...

Страница 1651: ...programmed differently Addresses I2S0_TCCR is 4002_F000h base 24h offset 4002_F024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DIV2 PSR WL DC PM W R...

Страница 1652: ...me rate dividers The divide ratio works on the word clock In Normal mode this ratio determines the word transfer rate In Network mode this ratio sets the number of words per frame The divide ratio ran...

Страница 1653: ...rammed differently Addresses I2S0_RCCR is 4002_F000h base 28h offset 4002_F028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 DIV2 PSR WL DC PM W Reset...

Страница 1654: ...der Control These bits are used to control the divide ratio for the programmable frame rate dividers The divide ratio works on the word clock In Normal mode this ratio determines the word transfer rat...

Страница 1655: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RFCNT1 TFCNT1 RFWM1 TFWM1 RFCNT0 TFCNT0 RFWM0 TFWM0 W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 I2Sx_FCSR field descriptions Field Desc...

Страница 1656: ...rved 0001 RFF set when at least one data word have been written to the Receive FIFO Set when RxFIFO 1 2 15 data words 0010 RFF set when more than or equal to 2 data word have been written to the Recei...

Страница 1657: ...smit FIFO empty is set when TxFIFO 11 data 0101 TFE set when there are more than or equal to 5 empty slots in Transmit FIFO default Transmit FIFO empty is set when TxFIFO 10 data 0110 TFE set when the...

Страница 1658: ...d in transmit FIFO 0001 1 data word in transmit FIFO 0010 2 data word in transmit FIFO 0011 3 data word in transmit FIFO 0100 4 data word in transmit FIFO 0101 5 data word in transmit FIFO 0110 6 data...

Страница 1659: ...RxFIFO 13 14 15data words 1110 RFF set when more than or equal to 14 data word have been written to the Receive FIFO Set when RxFIFO 14 15 data words 1111 RFF set when 15 data word have been written...

Страница 1660: ...here are more than or equal to 15 empty slots in Transmit FIFO default Transmit FIFO empty is set when TxFIFO 0 data 54 3 13 I2S AC97 Control Register I2Sx_ACNT Addresses I2S0_ACNT is 4002_F000h base...

Страница 1661: ...matically set This bit is automatically cleared by the I2S after completing transmission of a frame 0 Next frame will not have a Read Command 1 Next frame will have a Read Command 2 TIF Tag in FIFO Th...

Страница 1662: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx_ACDAT field descriptions Field Description 31 20 Reserved This read only field is reserved and always has the value zero 19 0 ACDAT AC97 Command Data The outgoing Comm...

Страница 1663: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 R TMSK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx_TMSK field descriptions Field Description 31 0 TMSK Transmit Mask These bits indicate...

Страница 1664: ...ed and always has the value zero 9 0 ACCST AC97 Channel Status These bits indicate which data slot has been enabled in AC97 variable mode operation This register is updated in case the core enables di...

Страница 1665: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 W ACCDIS Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2Sx_ACCDIS field descriptions Field Description 31 10 Reserved...

Страница 1666: ...in the first time slot of the frame No data transfers in subsequent time slots In normal mode TCCR DC values corresponding to more than a single time slot in a frame only result in lengthening the fra...

Страница 1667: ...a transmission period For a continuous clock the optional frame sync output and clock outputs are not disabled even if the receiver and transmitter are disabled 54 4 1 1 2 Normal mode receive The cond...

Страница 1668: ...is ready to transfer to the receive FIFO 0 The following figure shows transmitter and receiver timing for an 8 bit word in the first time slot in normal mode and continuous clock with a late word leng...

Страница 1669: ...the Rx data register In internal gated clock mode the Tx data line and clock output port are put in the high impedance state at the end of transmission of the last bit at the completion of the complet...

Страница 1670: ...of a new data frame Each data frame is divided into time slots and transmission and or reception of one data word can occur in each time slot rather than in just the frame sync time slot as in normal...

Страница 1671: ...sk registers TMSK and RMSK For using this mode of operation the CR TCHEN bit must be set 54 4 1 2 1 Network mode transmit The transmit portion of I2S is enabled when the CR I2SEN and TE bits are set H...

Страница 1672: ...nner as described above The only difference is interrupts related to the second channel are generated only if this mode of operation is selected ISR TDE1 is low by default 54 4 1 2 2 Network mode rece...

Страница 1673: ...ing for an 8 bit word with continuous clock FIFO disabled three words per frame sync in network mode Note The transmitter repeats the value 0x5E because of an underrun condition For the receive sectio...

Страница 1674: ...D or SRXD signals For this reason no frame sync is needed in this mode After transmission of data completes the clock is pulled to the inactive state Gated clocks are allowed for the transmit and rece...

Страница 1675: ...ses rising edge transition to clock data TCR TSCKP 0 and the falling edge transition to latch data RCR RSCKP 0 the clock must be in an active low state when idle If the I2S uses falling edge transitio...

Страница 1676: ...r 54 4 1 4 I2S mode The I2S is compliant to the Inter IC Sound I2S bus specification from Philips Semiconductors February 1986 Revised June 5 1996 The following figure depicts basic I2S protocol timin...

Страница 1677: ...RSCKP 1 Tx frame sync active low TCR TFSI 1 Rx frame sync active low RCR RFSI 1 Tx frame sync initiated one bit before data is transmitted TCR TEFS 1 Rx frame sync initiated one bit before data is re...

Страница 1678: ...1 Rx frame sync length set to one bit long frame RCR RFSL 1 Tx shifting w r t bit 0 of TXSR TCR TXBIT0 1 Rx shifting w r t bit 0 of RXSR RCR RXBIT0 1 Set the TCCR WL DC bits to configure the data tra...

Страница 1679: ...nabled the hardware internal overrides the following settings The programmed register values are not changed by entering AC97 mode but they no longer apply to the module s operation Writing to the pro...

Страница 1680: ...AC97 mode 1 Program the TCCR WL bits to a value corresponding to 16 or 20 bits The WL bit setting is only for the data portion of the AC97 frame slots 3 through 12 The tag slot slot 0 is always 16 bi...

Страница 1681: ...to see if the codec is ready If this bit is set the frame is received The received tag provides the information about slots containing valid data If the corresponding tag bit is valid the command addr...

Страница 1682: ...n transmission of an 8 10 12 16 18 20 22 or 24 bit word has completed The word clock then clocks the frame clock which counts the number of words in the frame The frame clock can be viewed on the STFS...

Страница 1683: ...smit section The serial bit clock can be internal or external depending on the TCR TXDIR bit The receive section contains an equivalent clock generator circuit Prescaler 1 or 8 Divider 1 to 256 TXDIR...

Страница 1684: ...ncy The oversampling clock frequency can go up to peripheral clock frequency Bits DIV2 PSR and PM must not be cleared at the same time I S 2 From this the frame clock frequency can be calculated Figur...

Страница 1685: ...3 7 1 256 8 16 4 12 288 0 0 11 7 3 512 8 16 1 12 288 0 0 31 7 0 192 12 16 2 12 288 0 0 15 7 1 384 12 16 4 12 288 0 0 7 7 3 768 12 16 1 12 288 0 0 23 7 0 256 16 16 2 12 288 0 0 11 7 1 512 16 16 4 12 28...

Страница 1686: ...2S master mode requires a 32 bit word length regardless of the actual data type Consequently the fixed I2S frame rate of 64 bits per frame word length TCCR WL can be any value and TCCR DC 1 are assume...

Страница 1687: ...rd length is less than 16 bits and msb alignment is chosen the most significant byte is bits 15 8 With lsb alignment the least significant byte is bits 7 0 Data alignment is controlled by the TCR TXBI...

Страница 1688: ...enable bit description If the receive FIFO is not enabled and the IER RIE and CR RE bits are set an interrupt occurs when the corresponding I2S receive data ready ISR RDR0 1 bit is set one value can b...

Страница 1689: ...is set a maximum of 15 values can be written to the I2S 15 per channel in two channel mode using Tx FIFO 1 When the IER TIE bit is cleared all transmit interrupts are disabled However the ISR TDE0 1 b...

Страница 1690: ...is cleared four clock cycles before the next frame an extra invalid frame is generated The following figure is an illustration of transmission case where TCR TXDIR and TCR TFDIR are set CR TE is clear...

Страница 1691: ...I2SEN bit which disables the I2S All other status and control bits in the I2S are affected as described in Memory map register definition I2S reset The I2S reset is generated when the CR I2SEN bit is...

Страница 1692: ...ated clock mode refer to Table 54 3 8 Set CR TE RE bits To ensure proper operation of the I2S use the power on or I2S reset before changing any of the I2S control bits listed in the following table No...

Страница 1693: ...N1 7 RFEN0 7 TFEN0 6 RFDIR 6 TFDIR 5 RXDIR 5 TXDIR 4 RSHFD 4 TSHFD 3 RSCKP 3 TSCKP 2 RFSI 2 TFSI 1 RFSL 1 TFSL 0 REFS 0 TEFS RCCR TCCR 16 WL3 15 WL2 14 WL1 13 WL0 ACNT 1 FV 10 5 FRDIV PHCONFIG 10 7 CL...

Страница 1694: ...Initialization application information K53 Sub Family Reference Manual Rev 6 Nov 2011 1694 Freescale Semiconductor Inc...

Страница 1695: ...GPIO input data register displays the logic value on each pin when the pin is configured for any digital function provided the corresponding port control and interrupt module for that pin is enabled...

Страница 1696: ...signal descriptions Signal Description I O PORTA 31 0 General purpose input output I O PORTB 31 0 General purpose input output I O PORTC 31 0 General purpose input output I O PORTD 31 0 General purpos...

Страница 1697: ...ion Any read or write access to the GPIO memory space that is outside the valid memory map results in a bus error All register accesses complete with zero wait states except error accesses which compl...

Страница 1698: ...ster GPIOB_PDIR 32 R 0000_0000h 55 2 5 1702 400F_F054 Port Data Direction Register GPIOB_PDDR 32 R W 0000_0000h 55 2 6 1702 400F_F080 Port Data Output Register GPIOC_PDOR 32 R W 0000_0000h 55 2 1 1700...

Страница 1699: ...on Register GPIOD_PDDR 32 R W 0000_0000h 55 2 6 1702 400F_F100 Port Data Output Register GPIOE_PDOR 32 R W 0000_0000h 55 2 1 1700 400F_F104 Port Set Output Register GPIOE_PSOR 32 W always reads zero 0...

Страница 1700: ...ed pin is configured for General Purpose Output 55 2 2 Port Set Output Register GPIOx_PSOR Addresses GPIOA_PSOR is 400F_F000h base 4h offset 400F_F004h GPIOB_PSOR is 400F_F040h base 4h offset 400F_F04...

Страница 1701: ...ding bit in PDORn does not change 1 Corresponding bit in PDORn is set to logic zero 55 2 4 Port Toggle Output Register GPIOx_PTOR Addresses GPIOA_PTOR is 400F_F000h base Ch offset 400F_F00Ch GPIOB_PTO...

Страница 1702: ...vice read as zero Pins that are not configured for a digital function read as zero If the corresponding Port Control and Interrupt module is disabled then that Port Data Input Register does not update...

Страница 1703: ...al purpose output The logic state of each pin can be controlled via the pin data output registers and pin output enable registers provided the pin is configured for the GPIO function If a pin is confi...

Страница 1704: ...Functional description K53 Sub Family Reference Manual Rev 6 Nov 2011 1704 Freescale Semiconductor Inc...

Страница 1705: ...iders 56 2 Features Support as many as 16 input capacitive touch sensing pins with individual result registers Automatic detection of electrode capacitance change with programmable upper and lower thr...

Страница 1706: ...PAD1 PAD15 Capacitance Measurement Unit NSCN PS EXTCHRG DELVOL REFCHRG TSICHnCNT STPE STM Electrode Scan Unit EOSF PEN 15 0 OVRF SMOD LPSCNITV Touch Detection Unit TSICHnLTH TSICHnHTH EXTERF OUTRGF To...

Страница 1707: ...Oscillator 16 bit Counter EXTCHRG DELVOL PS REFCHRG DELVOL Electrode Capacitance CAPTRM CLK EN Figure 56 2 TSI capacitance measurement unit block diagram 56 3 2 Electrode scan unit This section descri...

Страница 1708: ...e The upper and lower threshold values are configurable allowing the application to select the magnitude of the capacitance change to trigger the out of range flag With the threshold values programmed...

Страница 1709: ...and the MCU wake up In low power mode the electrode scan unit is always configured to periodical low power scan 56 4 4 Block diagram The following figure shows the block diagram of TSI module Cap Swi...

Страница 1710: ...capacity on board that will add to the system base capacitance 56 6 Memory map and register definition This section presents the touch sensing input module memory map and registers definition TSI mem...

Страница 1711: ...000h 56 6 6 1725 4004_512C Channel n threshold register TSI0_THRESHLD3 32 R W 0000_0000h 56 6 6 1725 4004_5130 Channel n threshold register TSI0_THRESHLD4 32 R W 0000_0000h 56 6 6 1725 4004_5134 Chann...

Страница 1712: ...S is 4004_5000h base 0h offset 4004_5000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R Reserved 0 LPCLKS LPSCNITV NSCN PS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6...

Страница 1713: ...es per electrode 00010 3 times per electrode 00011 4 times per electrode 00100 5 times per electrode 00101 6 times per electrode 00110 7 times per electrode 00111 8 times per electrode 01000 9 times p...

Страница 1714: ...or frequency divided by 128 15 EOSF End of scan flag Write 1 to clear the flag 14 OUTRGF Out of Range Flag Write 1 to clear the flag 13 EXTERF External electrode error occurred 0 No short 1 Short to V...

Страница 1715: ...while in low power modes STOP VLPS LLS and VLLS 3 2 1 0 Disable TSI when MCU enters low power modes 1 Allow TSI to continue running in all low power modes 56 6 2 SCAN control register TSIx_SCANC All S...

Страница 1716: ...0110 23 A charge current 10111 24 A charge current 11000 25 A charge current 11001 26 A charge current 11010 27 A charge current 11011 28 A charge current 11100 29 A charge current 11101 30 A charge c...

Страница 1717: ...00 25 A charge current 11001 26 A charge current 11010 27 A charge current 11011 28 A charge current 11100 29 A charge current 11101 30 A charge current 11110 31 A charge current 11111 32 A charge cur...

Страница 1718: ...ster TSIx_PEN NOTE Do not change PEN when GENCS TSIEN is set NOTE All PEN bits can be read at any time but must not be written while GENCS SCNIP is set Addresses TSI0_PEN is 4004_5000h base 8h offset...

Страница 1719: ...TSI_IN 15 is active in low power mode 15 PEN15 TSI pin 15 enable 0 The corresponding pin is not used by TSI 1 The corresponding pin is used by TSI 14 PEN14 TSI pin 14 enable 0 The corresponding pin is...

Страница 1720: ...in is used by TSI 4 PEN4 TSI pin 4 enable 0 The corresponding pin is not used by TSI 1 The corresponding pin is used by TSI 3 PEN3 TSI pin 3 enable 0 The corresponding pin is not used by TSI 1 The cor...

Страница 1721: ...is generated Write a one to clear this bit 30 ERROF14 TouchSensing Error Flag 14 This bit indicates when the corresponding electrode is shorted to VDD or VSS If the GENCS ERIE bit is set an error inte...

Страница 1722: ...nsing Error Flag 4 This bit indicates when the corresponding electrode is shorted to VDD or VSS If the GENCS ERIE bit is set an error interrupt is generated Write a one to clear this bit 19 ERROF3 Tou...

Страница 1723: ...this bit 8 ORNGF8 Touch Sensing Electrode Out of Range Flag 8 This bit indicates when the corresponding electrode is out of range If the GENCS TSIIE bit is set and the GENCS ESOR bit is cleared an ou...

Страница 1724: ...base 100h offset 4004_5100h TSI0_CNTR3 is 4004_5000h base 104h offset 4004_5104h TSI0_CNTR5 is 4004_5000h base 108h offset 4004_5108h TSI0_CNTR7 is 4004_5000h base 10Ch offset 4004_510Ch TSI0_CNTR9 i...

Страница 1725: ...cillator has its frequency dependable on the external electrode capacitance and the TSI module configuration After going to a configurable prescaler the TSI electrode oscillator signal goes to the inp...

Страница 1726: ...he electrode capacitance charging and discharging with a programmable current Electrode Voltage Time Electrode Capacitor Charging and Discharging with constant current Hysteresis Voltage Delta Figure...

Страница 1727: ...field GENCS NSCN defines the number of scans for each external electrode The pin capacitance sampling time is given by the time the module counter takes to go from zero to its maximum value defined b...

Страница 1728: ...trolled by the SCANC REFCHRG The reference oscillator frequency is given by the following equation Fref_osc Iref 2 Cref V Figure 56 69 Equation 4 TSI reference oscillator frequency Where Cref Internal...

Страница 1729: ...scans This feature is very useful for initialization of the touch application to detect the initial electrode capacitances This module generates configurable end of scan interrupt to indicate the app...

Страница 1730: ...SI active mode and TSI low power mode It has a separate scan period control for each one of these modes It allows the application to controls the trade off of the scan frequency and the average TSI mo...

Страница 1731: ...Upon the end of scan event each electrode conversion result will be loaded to the corresponding counter register compared with each threshold to determine if its value is out of range specified by th...

Страница 1732: ...the end of each electrode conversion the touch detection unit compares if the TSICHnCNT result value is inside a configurable range The comparison range is defined individually for each TSI pin by th...

Страница 1733: ...ion information After enabling the TSI module for the first time it is highly recommended to calibrate all the enabled channels by setting proper high and low threshold value for each active channel A...

Страница 1734: ...Application information K53 Sub Family Reference Manual Rev 6 Nov 2011 1734 Freescale Semiconductor Inc...

Страница 1735: ...ftware configuration the LCD panels can be either 3 V or 5 V The LCD controller also has several timing and control settings that can be software configured depending on the application s requirements...

Страница 1736: ...regulated power supply option for 3 V or 5 V LCD glass External VLL3 power supply option Internal regulated voltage source with a 4 bit trim register to apply contrast control Integrated charge pump...

Страница 1737: ...an LCD panel in Stop mode and the LCD controller continues to display the current LCD panel contents based on the LCD operation prior to the Stop event If the LCD is enabled in Stop mode the selected...

Страница 1738: ...s several external pins dedicated to power supply and LCD frontplane backplane signaling The LCD controller can be configured to support up to eight backplane signals This table lists and describes th...

Страница 1739: ...VSUPPLY 1 0 bits explanation 57 2 3 Vcap1 Vcap2 The charge pump capacitor is used to transfer charge from the input supply to the regulated output Use a ceramic capacitor A 0 1 F capacitor should be p...

Страница 1740: ...1752 400B_E028 LCD waveform register LCD_WF11TO8 32 R W 0000_0000h 57 3 9 1752 400B_E02C LCD waveform register LCD_WF15TO12 32 R W 0000_0000h 57 3 10 1753 400B_E030 LCD waveform register LCD_WF19TO16...

Страница 1741: ...ge can be used to generate a reference signal to the LCD charge pump for 3 V or 5 V LCD operation dependant on the HREFSEL bit NOTE The reset value of this register depends on the reset type POR 0x083...

Страница 1742: ...pump is selected Resistor network disabled The internal 1 3 bias is forced 22 HREFSEL High reference select When using the VIREG inputs this bit configures internal circuits to supply VLL1 0 Divide i...

Страница 1743: ...e VLL2 internally from VDD 01 Drive VLL3 internally from VDD 10 Reserved 11 Drive VLL3 externally from VDD or drive VLL1 internally from VIREG 15 LCDIEN LCD frame frequency interrupt enable Enables an...

Страница 1744: ...ally 1 LCD controller driver system is enabled and frontplane and backplane waveforms are generated All LCD pins LCD_Pn enabled using the LCD pin enable register output an LCD driver waveform The back...

Страница 1745: ...CD_AR is 400B_E000h base 4h offset 400B_E004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LCDIF 0 BLINK...

Страница 1746: ...k display mode Asserting this bit clears all segments in the LCD display 0 Normal or alternate display mode 1 Blank display mode 4 Reserved Reserved This read only field is reserved and always has the...

Страница 1747: ...only field is reserved and always has the value zero 14 12 FDPRS Fault detect clock prescaler Fault detect sample clock frequency is 0 1 1 bus clock 1 1 2 bus clock 2 1 4 bus clock 3 1 8 bus clock 4...

Страница 1748: ...enable Enable backplane timing for the fault detect circuit FDBPEN 0 generates frontplane timing This bit specifies the type of pin selected under fault detect test 0 Type of the selected pin under f...

Страница 1749: ...etect sample window 0 No one samples 1 1 one samples 2 2 one samples 254 254 one samples 255 255 or more one samples The FDCNT can overflow Therefore FDSWW and FDPRS must be reconfigured for proper sa...

Страница 1750: ...rs before enabling the LCD controller NOTE The reset value of this register depends on the reset type POR 0x0000_0000 Addresses LCD_BPENL is 400B_E000h base 18h offset 400B_E018h LCD_BPENH is 400B_E00...

Страница 1751: ...e operation the bits in WFn activate or deactivate each of the backplane phases connected to LCD_Pn bit 0 controls phase A bit 1 controls phase B and so on Software can write to this register with 8 b...

Страница 1752: ...400B_E024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WF7 WF6 WF5 WF4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_WF7TO...

Страница 1753: ...for WF3TO0 WF3 7 0 WF8 Controls segments or phases connected to LCD_P8 as described above for WF3TO0 WF3 57 3 10 LCD waveform register LCD_WF15TO12 See the LCD waveform register WFC3TO0 for register a...

Страница 1754: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WF19 WF18 WF17 WF16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_WF19TO16 field descriptions Field Description 31 24 WF19 Control...

Страница 1755: ...form register LCD_WF27TO24 See the LCD waveform register WFC3TO0 for register and field descriptions NOTE The reset value of this register depends on the reset type POR 0x0000_0000 Address LCD_WF27TO2...

Страница 1756: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_WF31TO28 field descriptions Field Description 31 24 WF31 Controls segments or phases connected to LCD_P31 as described above for WF3TO0 WF3 23 16 WF30 Controls segmen...

Страница 1757: ...waveform register WFC3TO0 for register and field descriptions NOTE The reset value of this register depends on the reset type POR 0x0000_0000 Address LCD_WF39TO36 is 400B_E000h base 44h offset 400B_E...

Страница 1758: ...nts or phases connected to LCD_P42 as described above for WF3TO0 WF3 15 8 WF41 Controls segments or phases connected to LCD_P41 as described above for WF3TO0 WF3 7 0 WF40 Controls segments or phases c...

Страница 1759: ...e 50h offset 400B_E050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WF51 WF50 WF49 WF48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 1760: ...for WF3TO0 WF3 7 0 WF52 Controls segments or phases connected to LCD_P52 as described above for WF3TO0 WF3 57 3 21 LCD waveform register LCD_WF59TO56 See the LCD waveform register WFC3TO0 for register...

Страница 1761: ...28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R WF63 WF62 WF61 WF60 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_WF63TO60 field descriptio...

Страница 1762: ...it in the BPENn is set the associated pin operates as a backplane The WFyTOx registers can then activate display the corresponding LCD segments on an LCD panel The WFyTOx registers control the on off...

Страница 1763: ...en number of frontplane pins In static mode only one backplane is required In multiplexed mode the LCD waveforms are multi level and depend on the bias mode Multiplex mode depending on the number of b...

Страница 1764: ...controller base clock and frame frequency The LCD controller is optimized to operate using a 32 768 kHz clock input Two clock sources are available to the LCD controller which are selectable by config...

Страница 1765: ...equency is too low or ghosting LCD controller frame frequency is too high To avoid these issues an LCD controller frame frequency in the range of 28 to 58 Hz is required LCD controller frame frequenci...

Страница 1766: ...1 4 1 5 1 6 1 7 1 8 Y 16 8 5 4 3 3 2 2 LCLK 2 0 0 76 3 76 3 81 4 76 3 81 4 67 8 87 2 76 3 1 61 61 65 1 61 65 1 54 3 69 8 61 2 50 9 50 9 54 3 50 9 54 3 45 2 58 1 50 9 3 43 6 43 6 46 5 43 6 46 5 38 8 49...

Страница 1767: ...1 1 2 Duty multiplexed with 1 3 bias mode low power waveform Duty 1 2 DUTY 2 0 001 LCD_P 1 0 enabled as backplanes BPEN0 1 and BPEN1 1 in the BPEN0 LCD_P0 assigned to Phase A WF0 0x01 LCD_P1 assigned...

Страница 1768: ...Phase Figure 57 29 1 2 Duty and 1 3 bias low power waveform 57 4 1 4 2 1 4 Duty multiplexed with 1 3 bias mode low power waveform Duty 1 4 DUTY 2 0 011 LCD_P 3 0 enabled as backplanes BPEN0 0x0F LCD_...

Страница 1769: ...1 VLL1 VLL1 VLL3 VLL3 0 0 0 0 0 0 0 Frame Interrupt Figure 57 30 1 4 Duty and 1 3 bias low power waveform 57 4 1 4 3 1 8 Duty multiplexed with 1 3 bias mode low power waveform Duty 1 8 DUTY 2 0 111 LC...

Страница 1770: ...e E WF4 0x10 LCD_P5 assigned to Phase F WF5 0x20 LCD_P6 assigned to Phase G WF6 0x40 LCD_P7 assigned to Phase H WF7 0x80 WF7TO4 0x80402010 WF3TO0 0x08040201 Functional description K53 Sub Family Refer...

Страница 1771: ...3 VLL3 VLL3 VLL3 VLL3 VLL3 VLL3 VLL3 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 VLL1 0 0 0 0 0 0 0 0 0 0 0 LCD_P5 BP5 LCD_P6 BP6 LCD_P7 BP7 LCD_P4 BP4 Base_Clk 1 Frame WFn 0x69 BP1 FP...

Страница 1772: ...ate LCD_P0 with backplane phase A WF3to0 0x00000001 This configures LCD_P0 to operate as a backplane that is active in phase A For LCD pins enabled as a frontplane Writing 1 to a given WF location res...

Страница 1773: ...egisters Table 57 34 Alternate display backplane sequence Duty Backplane sequence Alt backplane sequence 1 1 A E 1 2 A B E F 1 3 A B C E F G 1 4 A B C D E F G H 57 4 3 1 LCD blink modes The blink mode...

Страница 1774: ...the LCD controller blink frequency The LCD controller blink frequency is equal to the LCD clock LCLK divided by the factor selected by the BRATE 2 0 bits The following table shows LCD controller blin...

Страница 1775: ...VDD Upon Reset the VSUPPLY 1 0 bits are configured to connect VLL3 to VDD This configuration should be changed to match the application requirements before the LCD controller is enabled VLL1 VLL2 VLL3...

Страница 1776: ...n VDD connected to VLL3 internally derived from a regulated voltage source that can be configured to supply 1 0 or 1 67 V VIREG The following table provides a more detailed description of the power st...

Страница 1777: ...L2 11 X 1 0 VLL3 is driven externally for 3 V LCD glass operation Resistor Bias Network enabled For 3 V glass operation VLL3 must be equal to 3 V Charge pump is disabled Resistor Bias network is used...

Страница 1778: ...ulated voltage VIREG can be used as an input to generate the LCD bias voltages In this state external voltage source should not be connected to VLL1 VLL2 or VLL3 VIREG is controlled by the LCD general...

Страница 1779: ...tch option VSUPPLY 1 0 VDD switch option Recommend use for 3 V LCD panels Recommend use for 5 V LCD panels 00 VLL2 is generated from VDD Invalid LCD configuration VLL1 1 67 V VDD VLL2 3 3 V VLL3 5 V 0...

Страница 1780: ...off result in an erroneous information that can mislead a user and cause a dangerous situation The LCD Display Fault Detect circuit s LFD function finds faults in the LCD display display connector and...

Страница 1781: ...ent iben 0 1 oben 1 0 VSS VSS VSS VSS pull up pull up pull up pull up pull up VSS Vt VDD VDD VDD Rpull up Csegments Figure 57 33 Pullup fault detect in connection segment normal case Chapter 57 LCD Co...

Страница 1782: ...up pull up pull up pull up VSS VDD Csegments t Vt Vdd If there s any open case in connection or panel the Csegments will become smaller which makes the pull up time less Figure 57 34 Pullup fault dete...

Страница 1783: ...ference number This reference number is usually measured at the user s production facility by this circuit and stored for later comparison in the flash The comparison must account for fluctuations due...

Страница 1784: ...in connection or panel the Csegments becomes smaller which changes the rise time response Pullup fault detection can be performed while LCDEN is asserted 1 Set the target pin number by writing FDCR F...

Страница 1785: ...ID as front plane pin and all other FP pins PAD_Out all LCD pad FDCF FDEN Pull up detect wavefrom X reversed wavefrom for purpose of no DC 0 0 Tsww configure by FDSWW Tpull Tframe Tsample sample_clk 0...

Страница 1786: ...DPINID as back plane pin and all other BP pins PAD_Out all LCD pad FDCF FDEN Pull up detect wavefrom enable all BP LCD pins X reversed wavefrom for purpose of no DC 0 0 Tsww configure by FDSWW Tpull T...

Страница 1787: ...e The below list provides a recommended initialization sequence for the LCD controller You must write to all PEN BPEN and WFyTOx registers to initialize their values after a reset 1 GCR a Configure LC...

Страница 1788: ...details the register and bit field values required to achieve the appropriate LCD configuration for a given LCD application scenario The table below lists each example and the setup requirements Table...

Страница 1789: ...etup requirements for example 1 Example Operating voltage VDD LCD clock source LCD glass operating voltage Required LCD segments LCD frame rate Blinking mode rate Behavior in Stop and Wait modes LCD p...

Страница 1790: ...0 Hz LCD frame frequency see Table 57 31 DUTY 2 0 111 For 128 segments 8x16 select 1 8 duty cycle RVEN 0 VIREG is not used for this configuration RVTRIM 3 0 XXXX Trim value is determined by characteri...

Страница 1791: ...pin can be active in any phase 57 5 2 2 Initialization example 2 Example 2 LCD setup requirements are reiterated in the table below Table 57 44 LCD setup requirements for example 2 Example Operating v...

Страница 1792: ...ed to supply the LCD RVTRIM 3 0 XXXX Trim value is determined by characterization AR BLINK 1 Blinking is turned on or off during LCD operation ALT X Alternate bit is configured during LCD operation BL...

Страница 1793: ...0 11 When VSUPPLY 1 0 11 the LCD can be powered via VLL3 see Table 57 38 LCDIEN 0 LCD Frame Interrupts disabled LCDWAIT 0 LCD is off in Wait mode LCDSTP 0 LCD is off in Stop mode LCDEN 0 Initializati...

Страница 1794: ...the eight backplane pins are active in This configuration sets LCD_P0 to be active in Phase A LCD_P1 to be active in Phase B and so on This configuration sets LCD pins 0 7 to represent backplane 1 8...

Страница 1795: ...nergize WFyTOx Shown with 7 segment LCD glass hardware LCD_P 28 4 LCD_P 3 0 LCD Power Pins NOTE Configured for power using internal VDD Data Bus Segment Energize Segment Alternate Display Energize Dis...

Страница 1796: ...is done in the LCD waveform registers as shown below For this LCD controller any of the LCD pins can be configured to be Frontplane 0 2 or Backplane 0 2 For this example set LCD_P0 as FP0 LCD_P1 as FP...

Страница 1797: ...PB LCD_P1 BPA LCD_P1 BPC LCD_P2 BPB LCD_P2 BPA LCD_P2 Figure 57 40 LCD waveforms 57 6 1 2 Segment on driving waveform The voltage waveform across the f segment of the LCD between LCD_P4 BP1 and LCD_P0...

Страница 1798: ...ed when the LCD power supply is adjusted above and below the LCD threshold voltage The LCD threshold voltage is the nominal voltage required to energize the LCD segments For 3 V LCD glass the LCD thre...

Страница 1799: ...D GLASS PANEL NOTE Contrast control configuration when LCD is powered using internal VDD 5 5 V VDD is specified between 2 7 and LCD_P 28 8 LCD_P 7 0 Figure 57 43 Power connections for contrast control...

Страница 1800: ...Application information K53 Sub Family Reference Manual Rev 6 Nov 2011 1800 Freescale Semiconductor Inc...

Страница 1801: ...d connectivity while remaining transparent to system logic when not in test mode Testing is performed via a boundary scan technique as defined in the IEEE 1149 1 2001 standard All data input to and ou...

Страница 1802: ...several IEEE 1149 1 2001 defined instructions as well as several public and private device specific instructions Refer to Table 58 3 for a list of supported instructions Data registers bypass register...

Страница 1803: ...tion register while the JTAGC is enabled Supported test instructions include EXTEST HIGHZ CLAMP SAMPLE and SAMPLE PRELOAD Each instruction defines the set of data register s that may operate and inter...

Страница 1804: ...Clock Input TCK is an input pin used to synchronize the test logic and control register access through the TAP 58 2 2 TDI Test data input Test Data Input TDI is an input pin that receives serial test...

Страница 1805: ...ogic Reset TAP controller states Synchronous entry into the Test Logic Reset state results in the IDCODE instruction being loaded on the falling edge of TCK Asynchronous entry into the Test Logic Rese...

Страница 1806: ...ing table describes the device identification register functions Table 58 2 Device identification register field descriptions Field Description PRN Part Revision Number Contains the revision number of...

Страница 1807: ...determined by the value of the currently loaded instruction Data is shifted between TDI and TDO though the selected register starting with the least significant bit as illustrated in the following fig...

Страница 1808: ...R EXIT1 DR EXIT1 IR PAUSE DR PAUSE IR EXIT2 IR EXIT2 DR UPDATE DR UPDATE IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 58 4 IEEE 1149 1 2001 TAP controller finite state mac...

Страница 1809: ...9 1 2001 standard for more details All undefined opcodes are reserved Table 58 3 4 bit JTAG instructions Instruction Code 3 0 Instruction Summary IDCODE 0000 Selects device identification register for...

Страница 1810: ...o a reset state and forces the EZPORT mode select chip select low In this mode the flash can be programmed through the JTAG test port pins which are connected to the EZPORT module 58 4 4 3 SAMPLE PREL...

Страница 1811: ...off chip circuitry and board level interconnections by driving preloaded data contained in the boundary scan register onto the system output pins Typically the preloaded data is loaded into the bound...

Страница 1812: ...s for each pad are interconnected serially to form a shift register chain around the border of the design The boundary scan register consists of this shift register chain and is connected between TDI...

Страница 1813: ...egulator configurations Clarified the Wake up Sources section within the Low Leakage Wake up Unit LLWU Configuration section Renamed the LLWU inputs table to Wakeup sources for LLWU inputs removed the...

Страница 1814: ...clock diagram Updated the Internal clocking requirements section For the USB FS OTG Controller clocking section added this note The MCGFLLCLK does not meet the USB jitter specifications for certificat...

Страница 1815: ...to the appropriate pin names A 12 PORT changes No substantial content changes A 13 SIM changes Updated ADCxTRGSEL PFSIZE and EESIZE field descriptions A 14 Mode Controller changes In Modes of Operati...

Страница 1816: ...bstantial content changes A 23 EWM changes No substantial content changes A 24 WDOG changes Clarification added for no reset due to unlock sequence when ALLOW_UPDATE is cleared in Section Unlocking an...

Страница 1817: ...s 17 Swap indicator address not implicitly protected during Erase All Blocks command Erase All Blocks command erases program flash 1 IFR to uninitialize the swap system Modify swap command error handl...

Страница 1818: ...gain calibration values procedure Updated Pseudo code example section for CFG1 and SC2 register bits Removed band gap voltages BGH and BGL A 36 CMP changes Updated CMPx_CR1 PMODE field description A 3...

Страница 1819: ...tial content changes A 43 PIT changes No substantial content changes A 44 LPTMR changes Added note in LPTMR clocking section 7 Nov 2011 S Gallimore Added LPTPM_Doze_Yes condition for the latest versio...

Страница 1820: ...n added note on using TFFF flag Added links to corresponding functional description in the Delay fields in CTAR register Renamed DSICR to DSICR0 Updated EOQ interrupt request description Added SPITCF...

Страница 1821: ...ic register bit A 55 I2S changes Updated 1111 encoding for TFWM0 and TFWM1 bit fields A 56 GPIO changes No substantial content changes A 57 TSI changes No substantial content changes A 58 SLCD changes...

Страница 1822: ...K53 Sub Family Reference Manual Rev 6 Nov 2011 1822 Freescale Semiconductor Inc...

Страница 1823: ...pecifically disclaims any liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specification...

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