Table 5. J1003 pin definition (continued)
No.
Net name
Description
No.
Net name
Description
23
ECSPI2_SCLK
SPI2 clock signal
24
ECSPI2_SS0
SPI2 chip select signal
25
GND
Ground
26
—
NC
27
—
NC
28
—
NC
29
—
NC
30
GND
Ground
31
EXP_IO14
Expansion IO signal
32
EXP_IO12
Expansion IO signal
33
EXP_IO13
Expansion IO signal
34
GND
Ground
35
SAI5_RXD3
SAI5 receive data signal
36
SAI5_RXD2
SAI5 receive data signal
37
SAI5_RXD1
SAI5 receive data signal
38
SAI5_RXD0
SAI5 receive data signal
39
GND
Ground
40
SAI5_RXC
SAI5 receive clock signal
2.17 I2C connector (J1004)
One 8-pin dual-row Pin Header connector, J1004, is provided on the EVK board to support I
2
C connection. The developers can
use the port for some specific application development.
Table 6. J1004 pin definition
No.
Net name
Description
1/2
VDD_3V3
Power Output, 3.3 V
3/4
I2C3_SCL_3V3
I2C clock signal
5/6
I2C3_SDA_3V3
I2C data signal
7/8
GND
Ground
2.18 User interface buttons
There are two user interface buttons on the EVK.
2.18.1 Power button (SW901)
The i.MX 8M Nano UL Applications Processor supports the use of a button input signal to request main SoC power state changes
(i.e. ON or OFF) from the PMU.
The ON/OFF button can be used for debounce, OFF-to-ON time, and max timeout. Debounce is used to generate the power-off
interrupt. In the ON state, if ON/OFF button is held longer than the debounce time, the power-off interrupt is generated. In the OFF
state, if the ON/OFF button is held longer than the OFF-to-ON time, the state will transit from OFF to ON. Max timeout can also
be the time for requesting physical power down after the ON/OFF button has been held for the defined time.
NXP Semiconductors
Specifications
i.MX 8M Nano UltraLite DDR3L Evaluation Kit Hardware User's Guide, Rev. 0, March 2, 2021
User's Guide
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