NXP Semiconductors freescale MPC5668E, Руководство пользователя, Страница: 16 / 54

MPC5668EVB Users Manual Rev 0.1 May 2009
MPC5668EVBUM/D Page 12 of 29
3.3.2 Reset Buffering Scheme
The MPC5668 family has a single reset pin. This single pin functions as a dual purpose input / output signal,
providing Reset-In and Reset-Out functionality.
There is a lot of circuitry on the EVB that has access to the reset pin. In order to reduce the loading on the pin
(when the MCU is diving the reset signal) and also to allow connection of non open-drain reset inputs, a reset-
in and reset-out buffering scheme is implemented as shown in Figure 3-7.
Reset-In - There are 3 possible external sources of reset:
- JTAG / Nexus connector reset
-
User reset (from user connectors)
-
LVI reset circuitry, including the reset switch.
Each of these reset sources is fed into the input of an AND gate and then converted to an open-
drain output which is directly connected to the MCU reset pin.
Reset-Out - The MCU reset pin is buffered to provide a reset-out signal, capable of driving the reset LED and
also multiple devices requiring a reset input.
The reset buffering scheme is detailed below:
Figure 3-7 EVB Reset Buffering Scheme
Jumper J17 is used to completely disconnect the reset-in buffering if desired. This is for debug purposes only
and should normally be left connected. Disconnecting this jumper will mean no external MCU reset can be
achieved
Table 3-9 Reset-Out Control Jumper
Jumper Position PCB Legend Description
J68
(RST-IN)
FITTED (D) External reset source (LVI, Debug or Target) will be
able to assert MCU reset
REMOVED External reset is disabled ( Not recommended )
MCU
RESET
Reset OUT
From TGT
From JTAG / Nexus
From LVI (5v)
GND
Tri State Buffer
Reset IN
From LVI (3.3v)
J75
J68
(To RED Reset LED, BDM Reset In,
external device reset)
Reset OUT