NXP Semiconductors AN11524, Примечание к применению

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Application note Rev. 1 — 17 February 2015 35 of 54
NXP Semiconductors
AN11524
NXQ1TXA6 Evaluation Board
8.3 Power stage
Separate ground planes are used for the system ground (GND) and the power stage
ground (GNDI). It avoids crosstalk on sensitive signals which could otherwise result in
erratic system behavior.
It is important to tie the two ground planes together at only ONE point. Having several tie
points makes the purpose of separating the grounds useless. Do not have any other
non-related signals in the area of the power ground plane.
Keep the current loops, shown in green in Figure 22 , compact to minimize radiation. Place
the decoupling capacitor (C203), at the VDD supply pin of the NWP2081 (U201), close to
the IC.
Single the point system - power grounds
Fig 22. Half bridge driver stage of coil 1
aaa-015907
GNDI
GNDI
GNDI
+12 V
GNDI GNDI GNDI GND
NODEBRIDGE
Single tie point system to power ground
1
VDD
C203
C207
R206
R205
C208
n.c.
C211
L1-1
C210
C209
n.c.
R209
CL1T CL1C
COIL1T COIL1C
G
G
D
S
U201
GND
SD
CLK
GL
[1, 3, 4]
IS-
[1, 3, 4]
PWM_HIN
[1]
EN_HB1
[5]
UC1_2
SH
GH
FS
2
3
4
8
7
6
5
D
S
NWP2081
T203
T204
GNDI
C214
n.c.
C213
n.c.
GNDI
C216
GNDI
C217
C205 R203 T201
Fig 23. PCB layout of half-bridge driver of coil 1 in NXQ1TXA6 evaluation board
aaa-015908
single tie point for the system
and power grounds
compact current loops,
decoupling capacitors close by