Communication interfaces
A3M38SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, September 2022
Data Sheet: Technical Data
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9 Communication interfaces
The A3M38SL039 device contains a digital interface that supports either a 3-pin SPI or 2-pin I
2
C interface. The digital interface
is used to both read and write data to and from the device. The preferred interface type must be set at the factory prior to
shipment. For I
2
C functionality, order part number A3M38SL039I. For SPI functionality, order part number A3M38SL039S.
9.1 SPI
The A3M38SL039S can be programmed and the Tx bias settings and temperature read through the 3-pin SPI interface.
9.1.1 SPI timing diagram
The SPI interface timing of A3M38SL039S complies with SPI mode3 as shown in
Figure 5. Serial interface timing diagram
Table 16. Serial interface timing specification
Symbol
Parameter
Min (ns)
t
SC
Setup timing requirement of CS_B (both rising and falling) in relation to the rising edge of SCLK
50
t
WH
clk high duration
160
t
WL
clk low duration
160
t
SD
Date to clock rising edge setup
20
t
HD
clk rising edge to data hold time
20
t
HC
clk to CS_B hold time
50
t
WH
+
t
WL
Minimum clock period
400
9.1.2 SPI instruction set definition
The SPI instruction set is determined by the first byte after releasing the CS_B signal. The order of SPI instruction is MSB sent
first, LSB sent last. Bit 7 of the SPI instruction set is defined as read (1) or write (0) command. Bits 6
−
5 define the burst width
in the range of 1
−
4 bytes: 00 is for 1 byte data, 01 for 2 bytes data, 10 for 3 bytes data and 11 is for 4 bytes data. Bits 4
−
0 are
defined as the register address that is to be accessed.
