NXP Semiconductors A3M38SL039, Руководство пользователя

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Communication interfaces
A3M38SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, September 2022
Data Sheet: Technical Data 21 / 33
9.3.1 I 2 C SCLK and SDA characteristics
Table 19. I 2 C SCLK and SDA
Symbol Parameter Conditions Min Max Unit
f
SCLK
SCLK clock frequency — 0 400 kHz
t
HD;STA
Hold time (repeated) START condition
After this period, the first clock
pulse is generated.
0.6 — µs
t
LOW
Low period of the SCLK clock 1 — 1.3 — µs
t
HIGH
High Period of the SCLK clock — 0.6 — µs
t
SU;STA
Setup time for a repeated START condition — 0.6 — µs
t
HD;STA
Data hold time
2
BBUS-compatible masters — — µs
I 2 C bus devices 0 — µs
t
SU;STA
Data setup time — 100 3 — µs
t
r
Rise time of both SDA and SCLK signals — 20 300 ns
t
f
Fall time of both SDA and SCLK signals 4, 5, 6 — 6.5 300 ns
t
SU;STA
Setup time for STOP condition — 0.6 — µs
t
BUF
Bus free time between a STOP and START
condition
— 1.3 — µs
t
VD;DAT
Data valid time 7 — — 0.9 µs
t
VD;ACK
Data valid acknowledge time 6 — — 0.9 µs
1. Note: All values referred to V
IH(min)
(0.3 V
DD
) and V
IL(max)
(0.7 V
DD
) level.
2. t
HD:DAT
is the data hold time that is measured from the falling edge of SCLK and applies to data in transmission and the
Acknowledge.
3. A fast mode I 2 C bus device can be used in a standard mode I 2 C bus system, but the requirement t
SU:DAT
250 ns must then
be met. This is automatically the case if the device does not stretch the LOW period of the SCLK signal. If such a device
does not stretch the LOW period of the SCLK signal, it must output the next data bit to the SDA line t
r(max)
+ t
SU;DATA
=
1000 + 250 = 1250 ns (according to the Standard Mode I
2
C Bus Specification) before the SCLK line is released. Also the
Acknowledge timing must meet this setup time.
4. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
IH(min)
of the SCLK
signal) to bridge the undefined region of the falling edge of SCLK.
5. The maximum t
HD:DAT
could be 3.45 µs and 0.9 µs for standard mode and fast mode, but must be less than the maximum
of t
VD:DAT
or t
VD:ACK
by a transition time. This maximum must only be met if the device does not stretch the LOW period
(i
LOW
) of the SCLK signal. If the clock stretches the SCLK, the data must be valid by the setup mode before it releases the
clock.
6. t
VD;ACK
= time for Acknowledgement signal from SCLK LOW to SDA output (HIGH or LOW, depending on which one is
longer).
7. t
VD:DAT
= time for data signal from SCLK LOW to SDA output (HIGH or LOW, depending on which one is longer).