Basic description of PCL series
-4-
4. Pre-register (preliminary buffer for the next operation)
50oo (Except PCL5022/5023) 61oo 60oo
The term pre-register refers to a register used to prepare for operation.
Simply put, this is just like a waiting room where the data for the next speed pattern is stored.
As you can see in <Table 2> below, the pre-registers are provided primarily for registers that determine speed
patterns.
Registers that have pre-registers
Register name
Register details
PCL3013/5014 PCL6113/6123/6143 PCL6025/6045B
Feed amount (preset amount or target
position)
R0 RMV RMV
FL speed
R1
RFL
RFL
FH speed
R2
RFH
RFH
Acceleration rate
R3
RUR
RUR
Deceleration rate
R15
RDR
RDR
Speed multiplication rate
R4
RMG
RMG
Rampdown point
R5
RDP
RDP
Operation mode
Operation mode buffer
RMD
RMD
Center position during arc interpolation, or
main axis feed amount during linear
interpolation
- RIP
RIP
S-curve range during S-curve acceleration
RUS
RUS
S-curve range during S-curve deceleration
R16
(shared for both
acceleration /
deceleration)
RDS RDS
Start command
With preliminary buffer
<Table 2>
On the models that do not have pre-registers (PCD series, PCL-240 series, and PCL5022/5023), if you want to
use next different operating pattern after completing one operation, first the LSI confirms the end of the
previous operation using the INT signal or a status register. After confirming this, you have to write the data for
the next operation (preset amount, FL/FH speed, acceleration/deceleration rate, multiplication etc.) from a
CPU. If the register value is the same as in the previous operation, you only write the preset amount and any
other values you want to change. The time required to confirm the end of previous operation and write the data
for the next operation is only a few µs. However, this interval is simply waiting time before the ultimate
operation begins.
With pre-registers, you can write the data for the next operation during the current operation, so that the next
data are available as soon as they can be used. Then, the LSI can start the next operation immediately,
without the waiting time described above.
The operating pattern is a chain of multiple patterns, as shown in Figure 2.
During this interval, the LSI confirms that operation (1) has stopped and writes the register
values and commands for operation (2). Therefore, there is a period when everything stops,
even though it is very short. (The same is true for the time between operations (2) and (3), etc.)
- Without pre-registers
ｔ
ｆ
(1) (2)
(3)
<Figure 1>
