1450A/02-AH Manual
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Copyright 2003 Novatech Instruments, Inc.
10/5/2005
Operational Notes:
Upon power up or changing of the clock source, the internal clock generator may take up to one
minute to lock to within 0.1ppm of the 10MHz internal master clock or the external 10MHz. The
external clock must be 10MHz
±
5ppm and >1V
rms
into the 50
Ω
input impedance (square wave or
sinewave). A MR- restarts this timing period. The phase between the external clock input and any of
the synthesizer outputs is not controlled. During out-of-lock or during a lock acquisition time, the
front panel “LOCK” LED will be dark.
Delay Dispersion. Due to various propagation delays and anti-alias filter group delays, outputs set to
zero phase (delay) in the synchronous mode may be offset from the reference synthesizer
±
10ns. The
14-bit resolution of the phase control allows this to be accounted for and calibrated out by the user
application. This dispersion will vary with frequency. Note that equal lengths of ordinary coaxial
cable will have dispersion characteristics much greater that the resolution of the phase (delay) control
and this must be taken into account in the final application.
Changing the MODE via the control pin on the connector or by the rear panel switch will initiate a
MR- cycle. This ensures that all synthesizers are properly initialized.
Mechanical Notes:
The Model 1450A/02-AH is housed in a 19-inch, 2U rack, 18-inches deep. The rear panel photo is
Table 2: Timing, Synchronous Mode.
Parameter
Name
Min
Max
Notes
T
su
Binary Data Setup
25ns
Binary Data Stable before PFn or
CFS.
T
ld
CFS or PF Pulse
Width Low
100ns
Minimum CFS or PF pulse width.
T
b
Busy Time
1.3
µ
s
BUSY is HIGH for internal data
transfer.
T
nf
New Frequency Time
200ns
New frequency and phase on output.
T
cyc
Load cycle time
2.5
µ
s TYP
Cycle time before next CFS time.
T
disp
Delay Dispersion
-10ns
+10ns
Zero Phase Delay with respect to
reference synthesizer.
