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1450A/02-AH Manual

5/10

Copyright 2003 Novatech Instruments, Inc.

10/5/2005

MR- is the master reset signal (guaranteed for Factory Use Only). When LOW all the circuitry 
internal to the 1450A/02-AH is reset. Upon returning HIGH, the 1450A/02-AH will initialize in less 

than 250ms and output a frequency of 10.0MHz and 0

o

 phase. Toggling MR- performs the same 

function as cycling power. An internal reset is issued upon change of the MODE switch. MR- must be 
low for at least 1ms.

After a power cycle, mode change or MR-, the 1450A/02-AH takes approximately 500msec to 

Table 1: Timing, Independent Mode.

Parameter

Name

Min

Max

Notes

T

su

Binary Data Setup

25ns

Binary Data Stable before PFn.

T

ld

PF Pulse Width Low

100ns

Minimum PF pulse width.

T

b

Busy Time

430ns

BUSY is HIGH for internal data 
transfer.

T

nf

New Frequency Time

600ns

New frequency on output.

T

zd

Zero Decay Time

10

µ

s TYP

Time for Output to decay to ±100mV 
after setting frequency to zero (Sine 
output only). Square wave output may 
be erratic during this time.

T

d

Busy LOW to output

170ns

Time for new output to stabilize after 
BUSY returns LOW.

T

cyc

Load cycle time

600ns TYP

Cycle time before next PF.

Input (Independent Mode) Timing Diagram (Not to Scale)

T

su

T

ld

T

b

FREQ

n

FREQ

n+1

T

nf

FREQ

n+2

T

zd

PFn

FB

BUSY

OUT

T

cyc

Содержание 1450A/02-AH

Страница 1: ...locks to and tracks this input when present An internal TCXO 10MHz 2ppm is used if the 10MHz external clock input is left unconnected SMA Female PHASE and FREQUENCY CONTROL The Parallel interface is...

Страница 2: ...Y RESERVED F FB5 AR FB35 BZ RESERVED H FB6 AS FB36 CA RESERVED J FB7 AT FB37 CB RESERVED K FB8 AU FB38 CC RESERVED L FB9 AV FB39 CD RESERVED M FB10 AW FB40 CE RESERVED N FB11 AX FB41 CF RESERVED P FB1...

Страница 3: ...r your control signals depending upon your cabling The exact value will be determined by your application Reserved pins must be left unconnected except as noted here Three control pins are available R...

Страница 4: ...letion of the loading process a new frequency is available at the output The on board circuitry takes approximately 170ns to set the new frequency after BUSY has returned LOW The timing of BUSY return...

Страница 5: ...approximately 500msec to Table 1 Timing Independent Mode Parameter Name Min Max Notes Tsu Binary Data Setup 25ns Binary Data Stable before PFn Tld PF Pulse Width Low 100ns Minimum PF pulse width Tb B...

Страница 6: ...s propagation delays is greater than this and must be taken into account in the customer application PFR with PB0 through PB13 set to zero phase and FB0 through FB47 set to the desired frequency must...

Страница 7: ...e to account for capacitive loading on this signal Please refer to the timing diagram and table below for the details of setting frequency and phase on the parallel interface in the synchronous mode M...

Страница 8: ...accounted for and calibrated out by the user application This dispersion will vary with frequency Note that equal lengths of ordinary coaxial cable will have dispersion characteristics much greater t...

Страница 9: ...of the EDAC interface connector is in the upper left corner of the connector The connector without pins inserted is shown below I F Connector MOTHER BOARD DATA EXT 10MHz CLK SEL CLK GEN 10MHz INT 1 2...

Страница 10: ...vent shall seller be liable for collateral or consequential damages Some states do not allow limitations or exclusion of consequential damages so this limitation may not apply to you All instruments m...

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