1450A/02-AH Manual
7/10
Copyright 2003 Novatech Instruments, Inc.
10/5/2005
V
oh
>= 3.0 V (I
load
<= -100
µ
A)
V
ol
<= 0.4V (I
load
<= 100
µ
A)
BUSY going HIGH indicates that all parallel data is being loaded into the DDS circuitry and the new
frequency is unstable. The output frequency is updated approximately 170ns after the BUSY caused
by CFS pulses HIGH. The length of CFS LOW is not critical. Please refer to timing diagram for
details.
BUSY has a source resistance of approximately 100
Ω
to prevent damage due to accidental shorts. If
this output is used for handshaking, be sure to account for capacitive loading on this signal.
Please refer to the timing diagram and table below for the details of setting frequency and phase on
the parallel interface in the synchronous mode.
MR- is the master reset signal. When LOW all the circuitry internal to the 1450A/02-AH is reset.
Upon returning HIGH, the 1450A/02-AH will initialize in approximately 250ms with an output
frequency of 10.0MHz and 0
o
phase. Toggling MR- performs the same function as cycling power. A
reset is issued upon change of the MODE switch. MR- must be low for at least 1ms.
After a power cycle, mode change or MR-, the 1450A/02-AH takes approximately 250msec to
initialize.
Input (Synchronous Mode) Timing Diagram (Not to Scale)
T
su
T
ld
T
b
T
nf
PF0
BUSY
OUT
PB,
PF7
CFS
T
ld
PFn
FB
