Peak 602VL User's Guide
Rev. B0
Dec. 2000
BIOS Setup
4-13
Advanced Chipset Features Setup Menu
Since the features in this section are related to the chipset in the CPU board and all are optimized, you are
not recommended to change the default settings in the setup table, unless you know very detailed of the
chipset features.
This section allows you to configure the system based on the specific features of the installed chipset.
This chipset manages bus speeds and access to system memory resources, such as DRAM and the
external cache. It also coordinates communications between the conventional ISA bus and the PCI bus.
It must be stated that these items should never need to be altered. The default settings have been
chosen because they provide the best operating conditions for your system. The only time you might
consider making any changes would be if you discovered that data was being lost while using your system.
The first chipset settings deal with CPU access to dynamic random access memory (DRAM). The default
timings have been carefully chosen and should only be altered if data is being lost. Such a scenario
might well occur if your system had mixed speed DRAM chips installed so that greater delays may be
required to preserve the integrity of the data held in the slower memory chips.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM
timing.
The Choice: 2, 3
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle.
