NEC V850E/CA1 ATOMIC, Предварительное руководство пользователя

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Chapter 4 Bus Control Function
Preliminary User’s Manual U14913EE1V0UM00
4.5 Bus Access
4.5.1 Number of access clocks
The number of basic clocks necessary for accessing each resource is as follows.
Table 4-1: Number of Bus Access Clocks
4.5.2 Bus sizing function
The bus sizing function controls data bus width for each CS area. The data bus width is specified by
using the bus size configuration register (BSC).
(1) Bus size configuration register (BSC)
This register can be read/written in 16-bit units.
Cautions: 1. Write to the BSC register after reset, and then do not change the set value. Also, do
not access an external memory area other than that for this initialization routine
until initial setting of the BSC register is finished. However, it is possible to access
external memory areas whose initialization has been finished.
2. When the data bus width is specified as 8 bits, only the LWR signal becomes
active.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial
value
BSC 0 BS70 0 BS60 0 BS50 0 BS40 0 BS30 0 BS20 0 BS10 0 BS00 FFFFF066H 5555H
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
Bit Position Bit Name Function
15 to 0 BSn1, BSn0
(n = 0 to 7)
Data Bus Width
Sets the data bus width of CSn area.
BSn0 Data Bus Width of CSn area
0 8 bits
1 16 bits
Notes: 1. The instruction fetch becomes 2 clocks, in case of contention with data access.
2. This is the minimum value.
Resources (Bus width) Internal ROM
(32 bits)
Internal RAM
(32 bits)
Peripheral I/O
(16 bits)
External memory
(16 bits)
Bus Cycle Configuration
Instruction fetch Normal access
1
Note 1
1
Note 1
-
2
Note 2
Branch 2 1 -
2
Note 2
Operand data access 5 1
3
Note 2
2
Note 2