NEC V850E/CA1 ATOMIC, Предварительное руководство пользователя

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Chapter 13 FCAN Interface Function
Preliminary User’s Manual U14913EE1V0UM00
13.3 Control and Data Registers
13.3.1 Bit set/clear function
Direct writing of data (bit operations, read-modify write, direct writing of a target value) is not allowed to
few specific registers, where bit setting and bit clearing might be performed by CPU and by the FCAN
system. The following registers of the FCAN system are concerned.
• CAN global status register (CGST)
• CAN global interrupt enable register (CGIE)
• CAN global interrupt pending register (CGINTP)
• CAN x interrupt pending registers (CxINTP)
• CAN x control registers (CxCTRL)
• CAN x definition registers (CxDEF)
• CAN x interrupt enable registers (CxIE)
• CAN x bus activity registers (CxBA)
• ELISA status register (ELSR)
Remark: x = 1 to 3
Registers like above, where bit access and direct write operations are prohibited, are organized in such
a way that all bits allowed for manipulation are located in the lower byte (bits 7 to 0), while in the upper
byte (bits 15 to 8) either no or read-only information is located.
The registers can be read in the usual way to get all 16 data bits in their actual setting (ref. to appropri-
ated register description).
For setting or clearing any of the lower 8 bits the following mechanism is implemented:
When writing 16-bit data to the register address, each of the lower 8 data bits indicates whether the cor-
responding register bit should be cleared (data bit set) or remain unchanged (data bit not set). Each of
the upper 8 data bits indicates whether the corresponding register bit should be set (data bit set) or
remain unchanged (data bit cleared).
The organization of 16-bit data write for such registers is shown in Figure 13-7.