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CHAPTER 6 16-BIT TIMER 90
User’s Manual U15075EJ2V1UD
135
6.5.2 Restrictions on rewriting 16-bit compare register 90
(1) When rewriting the compare register (CR90), be sure to disable interrupts (TMMK90 = 1), and disable
inversion control of timer output (TOC90 = 0) first.
If CR90 is rewritten with interrupts enabled, an interrupt request may be generated at the point of rewrite.
(2) The interval time may be double the intended time depending on the timing at which the compare register
(CR90) is rewritten. Likewise, the timer output waveform may be shorter or double the intended output.
To avoid this, rewrite using one of the following procedures.
<Prevention method A> Rewriting by 8-bit access
<1> Disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0)
<2> Rewrite the higher byte of CR90 (16 bits) first
<3> Next, rewrite the lower byte of CR90 (16 bits)
<4> Clear the interrupt request flag (TMIF90)
<5> After more than half the cycle of the count clock has passed from the start of the interrupt, enable timer
interrupts and timer output inversion
<Program example A> (When count clock = 64/f
X
, CPU clock = f
X
)
TM90_VCT: SET1
TMMK90
;Timer interrupt disable (6 clocks)
CLR1
TMC90.3
;Timer output inversion disable (6 clocks)
MOV A,#xxH
;Higher byte rewrite value setting (6 clocks)
MOV !0FF17H,A
;CR90 higher byte rewriting (8 clocks)
MOV A,#yyH
;Lower byte rewrite value setting (6 clocks)
MOV !0FF16H,A
;CR90 lower byte rewriting (8 clocks)
CLR1 TMIF90
;Interrupt request flag clearing (6 clocks)
CLR1 TMMK90
;Timer interrupt enable (6 clocks)
SET1 TMC90.3
;Timer output inversion enable
Note
This is because the INTTM90 signal is set to the high level for a period of half the cycle of the count clock
after an interrupt is generated, so the output will be inverted if TOC90 is set to 1 during this period.
More than 32 clocks in
total
Note
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